09-28-2011 08:33 AM
I'm running the Virtex-6 Embedded Tri-Mode Etherent MAC wrapper design exemple on a ML605 platform (V1.5).
the exemple disign is working after small adaptations, but I have some questions about it.
the MAC ipcore datasheet say that the GMII connection with the PHY are constrained at 200Mhz to make sur that the signal will be good for 125Mhz (UG545 p80).
This is done by the IDELAYCTRL. This component take a 200Mhz clock ( REFCLOCK) constrained it 200Mhz on the ucf:
# IDELAYCTRL 200MHz reference clock
NET "REFCLK" TNM_NET = "clk_ref_clk";
TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50%;
# locate the 200 Mhz delay controller clock buffer
INST "refclk_bufg" LOC ="BUFGCTRL_X0Y7"
I have not putted some LOC constraints about this net in the TOP of the design but I have no errors when I generate the bitstream.
I open the design with FPGA-Editor and I have seen that REFCLOCK was placed at the I/O pin A10 of the FPGA, wich is an open pin on the platform.
so I am lucky that the design exemple is working ? what I need to do to make it clean?
I have to put a 200Mhz clock on the ref clock? I must left the REFCLOCK unconnected, it is just the timespec on the ucf the important parameter?
Thanks in advance for enlightning me.
09-30-2011 12:25 AM
I posted this in the wrong place.
But anyway I think the information about that is in the XAPP707 application note: advenced chipsync application.
10-03-2011 03:22 AM
it is not necessary to place 200Mhz clk on REFCLK signal as REFCLK is only required for RGMII.
With out REFCLK ur system will running well on GMII.