Virtex® Family FPGAs

[agaugue]

hello,

I have a design woking fine with a Virtex6 at speed -1:

  - 1.25Gbps DDR signals with 625Mhz clock

  - /4 deserialisation with Idelay / Idelay ctrl

  - 312.5Mhz clock in a BUFR feed by the 625Mhz clock.

I have recently seen in the DC & switching datasheet of the Virtex6 Fmax BUFR=300Mhz.

It seems a bit contradictory with the clocking resources guide which claims to use the BUFR over BUFG to capture synchonous data? and if not, why putting BUFR in the design while a BUFG can do best?

Regards

[avrumw · Accepted solution]

The BUFR and BUFG have different sets of functionalities. The combination of a clock capable I/O driving both a BUFIO and a BUFR (using division) is one of the preferred mechanisms of capturing a high speed input interface (like the one you are describing); the BUFIO drives the high speed clock of the ISERDES (CLK), and the BUFR drives the low speed clock (CLKDIV).

However, the FMAX of the BUFR is a real constraint, and in a -1 device, the maximum frequency is 300MHz. Thus this mechanism will only work if your low speed clock is below 300MHz. Given your freqencies, this would only be able to be done with deserialization rates greater than 4 (unless you go to a higher speed grade; the -2 is capable of 420MHz).

It is not an option to simply replace the BUFR with a BUFG. While the BUFG network is capable of higher frequencies, it cannot do the division of the BUFR, and, more importantly, will not provide the required phase relationship between CLK and CLKDIV at the ISERDES - the ISERDES will not function using BUFIO and BUFG.

Avrum