Virtex® Family FPGAs

[aruni]

Current Setup:

ML605 + FMC-105 expansion card.

I am currently using my setup to do a couple of test I/O projects. I am a bit confused about IOSTANDARDs. I would like to know if there is a way to get a different output voltage for a logical 1 on the FMC HPC pins.

When the IOSTD is set to LVCMOS25 as default, and I assign a 1 to a port, the output voltage is 2.5v. However, from what I understand (may be incorrect), I should be able to set the pins (all in the same bank) to, say, LVCMOS18, and get a 1.8v output = logical 1.

I created a simple test project that contained only an output port assigned to 1'b1 (in ISE). I then constrained the port to a pin on the FMC connector with an IOSTD of LVCMOS18. When I synthesize the design and load it into PlanAhead, PlanAhead reports that the pin connected is in bank 12, and that Vcco of that bank is 1.8v, as I would expect.

However, measuring the actual voltage on the pin yields 2.5v.

I have read numerous forum posts regarding this issue, including this one:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Xilinx-Virtex-6-ML605-Board-FMC-connector-IO-standar...

It was posted there that this is not possible, but if this is the case, then why does PlanAhead report as it does (and no warnings or errors are given of any kind during the synthesis/par/bitgen process)?

If someone could shed some light on this situation it would be much appreciated.

Thank you, and have a great day.

[eteam00]

I would like to know if there is a way to get a different output voltage for a logical 1 on the FMC HPC pins.

See DS152, Table 7.  The selection for highest output voltage (high) -- VOH -- is LVCMOS25, if you believe the datasheet.

-- Bob Elkind

[aruni]

Thanks for the quick reply.

Yes, I have viewed that table in DS152, and I agree that 2.5 is the maximum output voltage for a logical 1. However what I want is to set the pin so that it will output 1.8v as a logical 1 (less than the maximum, so it should be okay, right?)

In that table, LVCMOS18 and LVCMOS15 and even LVCMOS12 are listed there. However, when I attempt to set any of those as the IOSTANDARD for my output pins, I still measure 2.5 volts.

Even PlanAhead reports the Vcco for those banks as 1.8, 1.5, and 1.2 respectively. But the measurement disagrees. Is there any way to set a logical 1 as 1.8/1.5/1.2V?

[eteam00]

In that table, LVCMOS18 and LVCMOS15 and even LVCMOS12 are listed there. However, when I attempt to set any of those as the IOSTANDARD for my output pins, I still measure 2.5 volts.

That's correct.  VOH for these standards is referenced to VCCO (2.5V in this case), regardless of IO Standard selection.  DS152 Table 7 is pretty clear on this.

If you want 1.8V VOH, you should use a 1.8V VCCO supply.  Or some external components (translator, buffer, scaler, etc.).

-- Bob Elkind

[aruni]

So then, Vcco is not configurable? it is always at 2.5v?

PlanAhead reports that it can be changed. So then PlanAhead is incorrect?

I guess the question is, if a pin is set to LVCMOS18, then that does NOT automatically change Vcco to 1.8v for that bank, does it? How does one go about changing Vcco?

Thank you very much

[eteam00 · Accepted solution]

So then, Vcco is not configurable? it is always at 2.5v?

It's a power supply voltage connected to your FPGA VCCO pins.  It is not programmable in your code, or within ISE.  It's a hardware thing.  See the ML605 board schematics.

If the VCCO voltage is settable on the ML605 board, it will be set by way of jumpers or switches on the circuit board.

PlanAhead reports that it can be changed. So then PlanAhead is incorrect?

This is where you inform PlanAhead, so it understands which IO standard settings are available to the various IO banks of your design.  PlanAhead does not control or set the VCCO supply on the board.

-- Bob Elkind