Virtex® Family FPGAs

[austin]

Ed,

It also says that it you need the internal termination, the 100 ohms is only guaranteed to be within the tolerance for Vcc=2.5v.

I think this is very confusing...

The footnote referred to only implies that the differential input is powered from Vccaux, it doesn't mention that when Vcco=1.8v all standards are met.  And yet, there is anote that the internal termination may not meet spec if the Vcco isn't 2.5v.  If the internal termination is part of the receiver, then it is powered from Vccaux....

Of course, the voltages into the LVDS + and - inputs can not be greater than those allowed when Vcco=1.8 volts for reasons of relaibility.  But, does the LVDS standard ranges for the + and - outputs fall within our allowed range?  If not, we shouldn't suggest connection to an LVDS_25 input powered by 1.8v.

[mcgett]

Austin, I'm not sure what you are confused about.

The LVDS_25 input can be used with a VCCO of 1.8 and 2.5V in Virtex-6 (or lower the input voltage never exceeds the VCCO level, a sub-LVDS output would be an example where a lower voltage could be used)

Using the internal DIFF_TERM option requires that the VCCO of the bank be 2.5V as noted in UG361, so if you are using any other VCCO level simply use an external 100ohm termination resister.

[austin]

Ed,

OK.  If we just said what you just did, I am sure there would be no diffculty, but ug361 isn't as easy to understand (for me).

Thanks,

[eteam00]

...but ug361 isn't as easy to understand (for me).

Austin, perhaps you should open a webcase for this?  :)  (you knew this was coming when you wrote it, right?)

- Bob Elkind

[trent.jacobs]

austin.lesea : I was referring to Table 1-33, page 87 of UG361, as mcgett discovered.

Thanks for the good input.  I had not considered the variance in the value associated with diffterm as a function of VCCO.  Using an external 100Ohm termination resistor does seem to be the bulletproof choice.  We're looking into specifications on the variance of diffterm value as a function of VCCO to see if that is also a viable option.

-- edit --

I see that austin indicates the diffterm will not be in spec for VCCO != 2.5V.  We're keeping that in mind while we work on this, planning to default to external termination.

[austin]

t,

If you obtain the hspice model (encrypted) you can simulate exactly what will happen over process corners, temperature, and voltage to this 'resistor.'  I suspect it is highly non-critical.  If you place anywhere from 50 to 200 ohms termination in the simulator of the signal integrity, I doubt it makes any difference.

But data sheets are data sheets, and spec are specs:  I understand we can't claim standards compliance over too many variables varying.

I think we can get overly obsessed with details.  Signal integrity is important, and it needs to be verified, but matching +/- .x ohm is never required....

I think you gain a lot from use of the internal resistor primarily because there is no capacitive or inductive elements at play:  it is just a lot cleaner.  If it were me, I would find a way to continue to use the internal termination (simulate, find where it breaks, and then avoid going to that place).