Virtex® Family FPGAs

[pmeyeratdatest]

I am looking for any guidance on how to "fake" out the electrical requirements to DC couple a LVDS transmitter at 1.8V to a Virtex-5 IO. 

At the moment, I am thinking of enabling the Virtex I/O with a  DIFF_HSTL_I_DCI_18  I/O configuration  VREF will be set to 0.95V, VRN through 100 ohms to ground, VRP through 100 ohms to VCCO. 

Thoughts?

[austin]

p,

LVDS is a standard, with a specified Vcm, and Vdiff.  It is no different when you power the interface chips from 1.8, 2.5 or 3.3v (if they are standard drivers and receivers, the Vcc does not matter -- as long as it is what is specified for those chip).

So, a 1.8v powered standard LVDS driver chip (not a Xilinx product) drives any LVDS standard interface, regardless of the Vcc to that chip.

In the case of V5, the Vcco = 2.5 v for proper LVDS operation.

[pmeyeratdatest]

Hi Austin:

Thanks for replying.

So if I understand your comments, I can take  a 1.8v powered standard LVDS driver chip (not a Xilinx product), and drive Xilinx LVDS_25 receiver.

So you are saying that both driver and receiver have common Vref levels.

Regards,

Peter

[austin]

p,

Correct:  LVDS is a standard.  Vcm and Vdiff are unchanged.

[sameer120]

Hi Austin,

        We are Developing one product in that we are using the Spartan 3AN  XC3S400AN FGG400 -4C, In this would like to interface the Xilinx FPGA to a High Speed ADC using LVDS interface

1. Xilinx FPGA LVDS specifies the Voltage Levels of 2.5V & 3.3V as like LVDS25 & LVDS33

2. High speed ADC(ADS62P29) Specifies the Voltage Levels of 1.8V

So we would like to confirm that this interface will work fine without any issue?

Also we would like to know if any additional circuit needs to be added in the design

Please replay at earliest as its very critical phase of our design

Anticipating the needful

Thanks & Regards

Sameer Shirgaonkar

[cribbing]

Hi Sameer,

Honestly, the only way that you can be sure is to run the simulations.  Download our IBIS models (http://www.xilinx.com/support/download/index.htm)

Run the simulation and verify that everything matches up correctly.  If you are worried about your design not matching up properly, simulation is the only option that you can use to be sure.  

Carl

[austin]

Carl,

I have already stated (many times) LVDS is a standard, and if both chips comply, then connecting them works (regardless of Vcc).

And Carl, you are right:  simulation will show it works.  IBIS is as good as hspice in this case, so a Hyperlynx sim of the ADC connected to the FPGA will also tell if this will work.  Xilinx hspice and IBIS models are as good as a data sheet number:  they are guarantees of performance.

The key is:  is the ADC LVDS standard, or not?

[trent.jacobs]

On Virtex6 devices, LVDS_25 is the only LVDS IO standard listed in the user guide.  Note (1), in UG361 says that "differential inputs and inputs using VREF are powered from VCCAUX...".  I believe this means that LVDS_25 can be instantiated for LVDS reception in a bank with 1.8V VCCO, for instance, because LVDS will not exceed this VCCO.  Can you confirm that this is the correct interpretation?  If this is false, it is not apparent how to instantiate an LVDS receiver in a non-2.5V bank on V6 due to lack of any other LVDS IO type besides LVDS_25.

For reference, I am considering the converse situation as the grandparent post -- I would like to receive any LVDS-compliant signal in a bank that may not have VCCO set to 2.5V.   The LVDS driver feeding my FPGA bank may be operating off a 1.8, 2.5, or 3.3V supply, but will generate an LVDS-standard signal.

[austin]

t,

Not sure what you are reading:  V6 MUST use 2.5v Vcco for LVDS_25.

http://www.xilinx.com/support/documentation/user_guides/ug361.pdf

Page 84 (among others)

[mcgett]

> I believe this means that LVDS_25 can be instantiated for LVDS reception in a bank with 1.8V VCCO,

> for instance, because LVDS will not exceed this VCCO.  Can you confirm that this is the correct interpretation?

Yes, an IBUFDS_LVDS_25  or an IBUFDS with an IOSTANDARD property of LVDS_25 can be placed in a 1.8V or 2.5V bank and potentially a 1.5V if you can guarantee that the voltage on the pins will not exceed the 1.5V VCCO.

Table 1-33 in UG361 has this information.