Virtex® Family FPGAs

[jpowers@irvine-sensors.com]

In the code accompanying XAPP881, the IODELAYCTRL instantiation is driven by a 310MHz clock:

OVERSAMPLE_TOP.vhd, line 430:

        OVERSAMPLE_IDCTRL:IDELAYCTRL
        port map(
                RST=>MMCM_LOCKED_DELAY,
                REFCLK=>CLK310M,
                RDY=>RDY
        );

Yet in the IODELAYE1 instantiations, the reference clock frequency is listed as 208.33 MHz:

RX/OVERSAMPLE.vhd, line 119:

        ID_M:IODELAYE1
        generic map(
                IDELAY_TYPE=>"FIXED",
                IDELAY_VALUE=>0,
                HIGH_PERFORMANCE_MODE => TRUE,
                REFCLK_FREQUENCY=>208.333333)

I am confused -- is this a proper implementation? If so, then what does REFCLK_FREQUENCY specify if not the speed of the clock driving IODELAYCTRL?

Thanks,

Jonathan

[kren]

REFCLK_FREQUENCY is used by the timing analyzer for static timing analysis. The range of 290.0 to 310.0.