Virtex® Family FPGAs

[zhbeagle]

Hello,

I have generated IBERT Core for XUPV5 LX110T using IBERT core generator. In channel GTP_DUAL_X0Y5_0,  The link speed is  4.5 gbps and the Rx bit Error Ratio is about 3E-4. However,the speed of my SFP is just 2.5G, the speed of GTP is 3.125G.

How could it run to 4.5Gbps? I'm quite confused. By the way,why the bit error ratio could be so high?normally thebit error ratio should be 5E-12.

Any help will be greatly cherished.

Thanks in advance

[mcgett]

The Virtex-5 MGT can support line rates up to 6.5Gbps, but if you are using it outside of the data sheet specification for the speed grade of the device that you have and the components in the system then it won't work well (Niger BER).

[zhbeagle]

Thanks  for your reply and guidelines.

I set the speed to lower level,it seems to work well. But if I set the Max Line Rate in the core generator to 2000Mbps,the true speed on chip scope is about 3Gbps. And if I set the SATA lane in GTP_DUAL_X0Y3 to3000Mbps,it chould run to 4.5G. Why the true speed is faster than Max Line Rate?

By the way, the temperature of my chip is some high about 60 degrees,is it normal? or should i do something to lower it?In quartus2 ,we can set the unused pins to tri_stated,for example.

[mcgett]

The expected versus reported data rate is likely due to an error in the reference or system clock frequencies that you entered when generating the IBERT core versus the real frequencies on the board.

A junction temperature of 60C is well below the commercial temp maximum of 85C and it is not an issue. All unused IO will be tri-stated in the design by default in the design.

[zhbeagle]

Thank you very much Sir .