Virtex® Family FPGAs

[nankaimaxiang]

I can't find the pins of GTP/GTX which are showed in the ML505 manual.  How can I get it?.........

On the page 45 of the manual, the SFP FPGA Pin are G1 H1 F2 G2  (GTP0 of GTP_X0Y4). But I can't find the Pins in the planhead of the XC5VLX110T FF1136 in the ISE 13.4.

How can I solve it..........

[austin]

n,

The XUP board is noit a ML505!

Use the correct schematics:

http://www.xilinx.com/univ/xupv5-lx110t.htm

[nankaimaxiang]

I have connected the official website, and clicked the XUPV5 LX110T user manual. It said that "please refer to the ML505 user manual, and  the XUPV5-LX110T development system hosts a Virtex 5 LX 110T device. All other user interfaces remain the same."

I am really confused and angry about this.

[ywu]

I can see the MGT pins in your post in PlanAhead 13.4 (see the snapshot below). Note that there is a "Magnifier" button at the top left corner, where you can search for pins in your target device.

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nankaimaxiang wrote:

I can't find the pins of GTP/GTX which are showed in the ML505 manual.  How can I get it?.........

On the page 45 of the manual, the SFP FPGA Pin are G1 H1 F2 G2  (GTP0 of GTP_X0Y4). But I can't find the Pins in the planhead of the XC5VLX110T FF1136 in the ISE 13.4.

How can I solve it..........

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[austin]

n,

Sorry for the confusion.  The ML505 is similar, but not the same:  the ML505 has a LX50T, and the XUPV5 has a LX110T device.  So, the schematic of the board is different (schematics are there in the XUPV5 documentation).

Jim has pointed out where you may find the pins in the tools, and that works, too.

[nankaimaxiang]

thx a lot ,

then how to assign the bankless pins.....