Virtex® Family FPGAs

[murtaza5152]

Hi Guys,

I have come across some issues with the mapping process of Xilinx ISE. When I synthesize my design, i get some utilization of FPGA resources. Though when it is mapped to LUTs on the FPGA in the mapping process, all the utilization goes to 0%.!

It is very  much likely that his is being caused due to the design rather than the tool. I want to know, what are the typical cases in which such a thing is likely to happen. My top level design inputs the clock and just acts as a wrapper to encapsulate a bunch other self-independent blocks. Do i need to include some dummy ports in my top level modules that interface with the lower blocks?

Thanks.

[gszakacs]

Generally speaking, any signal in a design that does not affect an output pin will be removed during

the mapping phase.  I would suggest checking the option to create a "detailed" map report which

will allow you to see how the logic gets trimmed.  Normally this starts at the output end of the logic,

with nets that have no load, and works backwards.

If you're dealing with an incomplete design, a common practice is to create a function of all

your intermediate outputs that have no loads and run this function to one or more pins.  If

you only have a single pin, you can still use it to keep the entire design by making an XOR

of all nets with no load for example.  Another trick I often use when the design is incomplete is

to make a parallel-in serial-out shift register to bring signals to a single pin serially.  If you're

trying to see if the design will fit and meet timing, this latter approach may be easier to deal with.

-- Gabor

[murtaza5152]

So now I added a bunch of dummy signals to my top level module and hooked them up with a few internal signals and I see that the post-map output does show me utilization.

To confirm everything is mapped, i turned on the detailed report option for mapping. On carefully observing the report, i found out that the tool removes all those modules whose port signals do not map to the ports of the next higher level design. If if i have two modules using each other signals and not giving their outputs to the higher level output ports, both the modules are shelved. 

Does that mean i have to map all the internal signals between two modules to the higher-level module ports? 

[mcgett]

It isn't riduclous it is standard behaviour of all tool flows.  If something isn't used in a design then it is removed.  The tools work this way to save resources by removing unecessary logic.

[murtaza5152]

mcgett,

I bite my word. But can you please tell me whhow do i make the tool avoid that. Say i have two modules A & B which are encapsulated in a higher level module C. Now say if A generates some signal that is the input for B and B uses that signal to generate some other signal that is mapped to the output port of C. In this case what would happen is, A would be shelved off as the tool would see that A is not DIRECTLY influencing the outputs, though in reality it indirectly is.

How do I avoid removal of A? That is all my question.

(P.S: In no means i meant to demean the tool. :))

[mcgett · Accepted solution]

The module connectivity that you describe would not result in removal of the modules.

       +------------------------modC------------------+

       |                                              |

       |   +------modA------+   +------modB------+    |

       |   |                |   |                |    |

inC0-->|-->|inA0       outA0|-->|inB0       outB0|--->|-->outC0

inC1-->|-->|inA1       outA1|-->|inB1       outB1|--->|-->outC1

       |   |           outA2|-->|inB2            |    |

inC2-->|-->|inA2            |   |           outB2|--->|-->outC2

inC3-->|-->|inA3            |   |           outB3|--->|-->outC3

       |   |                |   |           outB4|    |

       |   +----------------+   +----------------+    |

       +----------------------------------------------+

Logic removal will happen if an output is unused and the logic will be trimmed backwards until it reaches a point where the logic is used for other portions of the design.  Errors should be generated if an input is undriven.

In the above ASCII art schematic, if outA[0:2] is a function of inA[0:3] and outB[0:3] is a function of inB[0:2] this logic will remain, but since outB4 is unused logic that feeds this from inB[0:2] would be deleted, but not the extent that it would impact outB[0:3].

If your logic is being removed it means that it is not being used.  Since, you think that this should not be happening you will need to go into your code and examine it again.