Virtex® Family FPGAs

[nairan]

Dear All,

I am using Xilinx ISE 10.1 project navigator. I used 'Add Copy of Source...' to move required .v, .xco and .ucf files to my working directory. Whenever I met a .xco file, I used CORE Generator to regenerate core (Here I was assuming all generated files would be automatically put into my working directory). Maybe I missed something but I cannot figure out what else I should do. Also I added all included files into my working directory.

Then I started XST to synthesize this design. The trouble was almost all (I guess it was all) generated modules cannot be identified, like this:
ERROR:HDLCompilers:87 - "rx_queue.v" line 162 Could not find module/primitive 'rxfifo_8kx9_to_72'

Anybody can help me with this? By the way, someone said this won't happen for newer versions of ISE, but my device is Virtex2Pro that is not supported by newer version.

Thanks,

[gszakacs]

If you run Core Generator from the ISE GUI, the default should be to place the generated files

in the same directory as the .xco file.  It's important that at least the .ngc file is in the project directory.

Normally when I want to copy a core to another project, I grab all the files that start with the core name,

for example rxfifo_8kx9_to_72*.*, and copy them to the new project directory.  There should also

be a rxfifo_8kx9_to_72_flist.txt file with the core that shows all generated files.

I've also had problems with some versions of ISE (I think 10.1 included) where after adding a

new core to a design, I needed to close and reopen the project before the core is properly added

to the hierarchy.  Newer versions of ISE have a "Force Hierarchy Reparse" menu item that

accomplishes the same thing.

-- Gabor