Virtex® Family FPGAs

[waris.mohammad]

Hi ,

       I am trying to make a 1MHz to 100Mhz varable oscillator using XC5VLX30T FPGA. The oscillator shall have 1MHz resolution.

       As i understand it may be feasible using DCM and dynamic recnfiguration of M &D values. I also came across XAPP872 which suggests the use of IODELAY to achieve a frerquency range of 82 MHz to 320MHz(lower frequencies can be achieved by dividing the input clock).

       Which one of these methods is better and easy to implement.

thanks

[rcingham]

Do you want a single-bit output (that is a 'clock' output), or mult-bit to send to a DAC?

What is the clock source on the board?

[waris.mohammad]

We want only single bit output tobe given to another block in the FPGA.

We will have a 50Mhz oscillator on the board.

[rcingham]

The simplest method that comes easily to mind is to use an internal PLL to multiply up to 200MHz, then a variable modulus counter/divider.

BTW, I suggest that count-down is better for variable modulus counters, so that you can have fixed comparison to 0.

[waris.mohammad]

Thanks for the reply.

Can you please elaborate on how to generate 1Mhz to 100Mhz using a down counter with a 200Mhz input clock.

regards

Mohammad waris

[rcingham · Accepted solution]

If you can't work out that sort of thing for yourself, perhaps you should consider a different occupation.

http://www.lmgtfy.com/?q=loadable+down+counter+VHDL

[waris.mohammad]

:)

U r so right ,I shuld have thought before asking.