Virtex® Family FPGAs

[dsugimura1]

I'm trying to implement a delay line using block RAM on a virtex 5. The delay line needs to delay the data for one clock cycle. Is this possible using block RAM?

I tried using a Simple Dual-Port RAM with 'read first' as the operating mode. I'm writing to one address and reading from it on the following clock. Then it takes another clock cycle for the data to be ready. Does anyone know if I could have the output ready sooner? If so, I'd be able to implement this delay line with one clock cycle delay. Currently, its appearing as a two clock cycle delay.

Thanks

[gszakacs]

I'm confused as to why you would use block RAM for a single-cycle delay.  Are you trying

to make a variable delay line that can have from 1 to N delay cycles where N is large?

If not block RAM does not make a lot of sense.  In any case I would think that you want

to "write first" if you want the lowest possible latency.  Remember that read and write

are both registered on a clock edge, but in write first mode, reading a cell while it is

being written returns the new data rather than the previous data.  I would simulate

this to see if it does what you need.

-- Gabor

[dsugimura1]

Thanks. 'Write-first' seems to do the job, although i'm getting a collision detection warning. I'm using Port A for writing. I have that mode as 'write-first' and I'm reading from port B where I'm using 'write-first' mode. Does it really matter what mode port B is in since I am only reading from it? I am using a simple dual port ram.

I would use registers instead of block ram, but I'm looking for ways to conserve flip-flops, so using ram for delay line was the other way I could think of.

[dsugimura1]

Thanks. 'Write-first' seems to do the job, although i'm getting a collision detection warning. I'm using Port A for writing. I have that mode as 'write-first' and I'm reading from port B where I'm using 'write-first' mode. Does it really matter what mode port B is in since I am only reading from it? I am using a simple dual port ram.

I would use registers instead of block ram, but I'm looking for ways to conserve flip-flops, so using ram for delay line was the other way I could think of.

[gszakacs · Accepted solution]

When your BRAM ports both use the same clock, you can generally ignore collision warnings

with the exception of write-write collisions, which won't happen if one port is read-only.

Generally an FPGA has a lot more flip-flops than block RAM, so it seems strange to use

BRAM to save flip-flops unless you have a very unusual design.  You can also use BRAM

to replace LUT's using a synthesis or map option.  If you really need a lot of flip-flops and

not so many LUT's, you can use LUT's as SRL16CE components to replace some flip-flops.

Just implementing a one (or more) cycle delay without a reset term will allow the tools to use SRL

automatically use LUT's if it will save resources.  Any register with a reset will generally

require a flip-flop instead.

-- Gabor

[dsugimura1]

Thanks Gabor for all the detailed information; it was VERY helpful.