06-09-2009 05:18 PM - edited 06-09-2009 05:21 PM
I want to gate the deskewed DCM clock output until the DCM is locked. What is the recommended way of doing this?
Looking at Figure 2-13 on page 78 of the Virtex-5 user guide, I am guessing that I can connect a BUFGCE to the CLK0 output of the DCM, with the DCM LOCKED output controlling the CE input of the BUFGCE. (The BUFGCE would be replacing the BUFGMUX in the figure, and I would keep a BUFG in the DCM feedback loop.)
Is this correct? I tried instanting this structure in a Verilog design, but Synplify Pro didn't seem to infer the derived clock after the BUFGCE correctly...
06-09-2009 07:00 PM
As a general rule you wouldn’t do that, there are exceptions to the rule, but not many.
Instead use an enable on you synchronous design and then use the locked signal to switch it on.
I’ve also used the locked signal to set a counter, then counted X pulses to set an enable, this gives you a variable start point..
06-09-2009 08:20 PM
Thanks for the suggestions, but I can't use a synchronous clock enable because I am prototyping a soft core (ASIC code) whose code I can't easily change. I also can't keep reset asserted until the DCM locks, because in this application the input clock to the DCM can be stopped for a long period of time and started up again without a reset. (I also need a circuit that resets the DCM whenever the input clock is stopped and restarted.)
The BUFGCE is supposed to guarantee that that the output clock is glitchless, so why is this method not recommended?
06-10-2009 03:14 AM
since the picture is from a XILINX user guide, I also think it's OK to do it this way if the other methods (CE or Reset) can't be applied.
Maybe it's just a tool problem. The synthesis tool has probably no idea that clock signals have to be treated special.
Try instantiating the desired element. And send a message to your Tool vendor about this, so the next version canbe improved.
Have a nice synthesis