>Can you give me some detai information about the chip's 12-layers
routing? So that we can rethink our solution.
If you were told you that a CLB tile had the following routing architecture
- 26 single vertical lines
- 14 single horizontal lines
- 16 hex vertical lines
- 12 hex horizontal lines
- 8 long vertical lines
- 8 long horizontal lines
how exactly would that help you in your developement process to obtain picosecond accuracy for your "phase difference measurement instrument"?
Note: the above list is a random set of numbers and lengths
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