I am a beginer on FPGA world, and
I am using XtremeDSP Development Kit-IV with virtex 4 and system generator 9.2i with simulink (2007)a
I am trying to design a simple filter by useing FIR compiler block but I always have this error
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: expected to find C:\XtremeDSP\mohamed\inoutADC\netlist\sysgen\coregen_jYxg/coregen_tmp/fir_compiler_virtex4_2_0_c5f31f35b9a2b830_flist.txt at C:\XtremeDSP\mohamed\inoutADC\netlist\sysgen\masterScript61668.pl line 578
Reported by:
Unspecified
can you please help me on that
I have attached the model
