Virtex® Family FPGAs

[aortega]

Hi! I'm a Student trying to make the ML507 iBERT work.

I have already generated the core using ibertgen, but when I connect with chipscope and select a RX rate of 6.5 Gpbs, it shows that 7.5 Gpbs is being transmitted by the GTX.

The same happen with other RX rates, selecting a 2.6 Gbps rate will produce a 3 Gbps rate, etc.

I have tested many configurations, including different coding (8b/10b), etc. All have resulted in a real data rate of about 20% more than the configured data rate.

What I'm doing wrong? I'm using the SATA crossover and Xilinx ISE 10.1 SP3.

Regards,

Alfredo

[mcgett]

When you configured the IBERT core, you must have entered the wrong frequency for the System Clock.

[zjz329]

I have the same problem. Does the frequency of the System Clock have some relationship with the frequency of  REFCLK ?

[mcgett]

The system clock is used as a timing reference to determine what the data and other clock rates are.

[aortega · Accepted solution]

Thanks mcgett! That solved my problem. My system clock was 150 Mhz, setting to 100 Mhz solved it.

Now iBert can't go past 6 GBPS but the data rate seems to be right.

Regards,

Alfred

[mcgett]

The ML507 is populated with a XC5VFX70T-FFG1136-1C device.  The -1 speed grade has a maximum GTX data rate of 4.25 Gbps

[aortega]

Hi mcgett.

I'm actually measuring 7.5 gbps at the output of a SFP on my ML507.

Ref. CLK==150 Mhz

Picture: http://ortegaalfredo.googlepages.com/screen1.png

That's the user pattern "0101-0101-0101-0101-0101", so you have a 3.75 GHz signal.

Other patterns works as expected. I'm triggering on the clk output (using only one output, not the differential. Maybe that's the reason of the high jitter?)