Virtex® Family FPGAs

[rubenverstraten]

Hello,

The iSerDes is used to deserialize high speed DDR input (10 bits @ 1.25 GHz -> 80 bits @ 156.25). The iSerDes outclock (clkdiv) is to be used as internal clock (Virtex 6), so as not to have to merge several clocktrees. So the clkdiv of the iSerDes IP LogiCore (created in ISE) is connected to a pll.

Settings of the iSerDes are:

No of IO's used: 10

Bus Direction: inputs

serialization factor: 8

Active clock edge: DDR

clock buffer used: BUFIO

Busiostd: LVCMOS18

The errormessage (design implementation) is as follows:

ERROR:NgdBuild:455 - logical net 'sbc_i/serdes_a_clk' has multiple driver(s):

Documentation that I searched so far:

- http://www.physics.ohio-state.edu/~gilmore/cms/datasheets/virtex-6-selectIO_ug361.pdf

- http://www.xilinx.com/support/documentation/application_notes/xapp721.pdf

In here is an example (figure 7) of how the user interface fifo's are to be implemented. But where does clkdiv_180 come from? Not from a different clocktree... I want to do it as in the attachment.

The Xilins forums did not seem to answer this problem...

Thanks in advance,

Ruben Verstraten

[rcingham]

Post the souce file that includes "logical net 'sbc_i/serdes_a_clk'".

[rubenverstraten]

Requested file attached

[roym]

Line 138 and 344 are both driving serdes_a_clk

        CLK_DIV_OUT         =>  serdes_a_clk,

 

Roy

[rubenverstraten]

Hello Roy,

The one is an output (serdes a), and the other is an input (pll) (Component instantiations). So what you say cannot be it.

The file only had 239 lines. It probably had something to do with line wrapping. Last time i could not append the file as .vhd so i added it as text.

I found that i needn't declare 4 identical components in order to initialize 4 component, so i corrected that and attached it to this message. In it:

line 99 - signal serdes_a is declared

line 134 - component serdes_a_i asserts its clk_div_out to serdes_a_clk

line 193 - component pll applies serdes_a_clk as input

? Is perfect

Ruben.

[rcingham]

Maybe the problem is in the 'serdes' block, or in whatever 'sbc' is instantiated into.

[rubenverstraten]

yes, that is what i thought. The problem is probably in the serdes block, but the problem is that it is a generated ip-core.

[rcingham]

If it is really there (check the HDL files to be sure!), then you will need to open a WebCase...

[rubenverstraten · Accepted solution]

Hello,

This case is solved now. I opened a webcase, and one of the Xilinx employees found the answer:

Hi Ruben, 

The issue is caused by the IBUFG (see screenshot bufg) which is generated with the PLL. This IBUFG is being driven by fabric as opposed to a pin. If you select "No Buffer" instead of "Single ended clock capable pin" when generating the PLL, no buffer is instantiated and no error occurs.

I hope this helps. 

Can you let me know if you have any further questions regarding case?

Kind regards,
Peadar

Thanks for helping me!

Cheers,

Ruben.