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med
Visitor
med
Posts: 24
Registered: ‎11-12-2010
0

problem with ODDR bloc

Hi,

 

 when I try to use the output of Oddr bloc as input to another component, the following error appears:

ERROR:Pack:2530 - The dual data rate register "DDR/ODDR_inst" failed to join an
   OLOGIC component as required.

 

What should I do so that I can use the output of Oddr as input for another component?


can someone help me please

Expert Contributor
gszakacs
Posts: 5,263
Registered: ‎08-14-2007
0

Re: problem with ODDR bloc

ODDR is an "Output" double-data-rate register.  As the name implies this can ONLY be used

as an output from the FPGA.  Any component downstream from this will therefore not be in

your design, but rather off-chip - like a DDR memory device.  The ONLY component you can

drive with the output of the ODDR is an OBUF or OBUFDS.

 

Perhaps if you describe what you are trying to do with this register we can help you find another

solution.

 

Regards,

Gabor

-- Gabor
med
Visitor
med
Posts: 24
Registered: ‎11-12-2010
0

Re: problem with ODDR bloc

 

 

In fact, I have to send two signals: a signal 'D' for data and a signal S '(with a simple XOR between the clock signal and the'D') hence the need to use output 'D' (which is the output of block Oddr)

Xilinx Employee
mcgett
Posts: 3,504
Registered: ‎01-03-2008
0

Re: problem with ODDR bloc

> In fact, I have to send two signals: a signal 'D' for data and a signal S '(with a simple XOR between

> the clock signal and the'D') hence the need to use output 'D' (which is the output of block Oddr)

 

First, the only connection that the output of the ODDR can make is to an output buffer it cannot be used in any other way.

Second, this doesn't make sense.

 

You have instantiated an ODDR register that has two data bits connected to D1 and D2 and clocked by your CLOCK net. I can't conceive of why you would need to XOR the output with the same CLOCK net that is driving it to create your "S" signal.

 

Since D1 will be clocked out on the rising edge of the CLOCK net an XOR with the value would simply by !D1.

Since D2 will be clocked out on the falling edge of the CLOCK net an XOR with the value would simply by D2.

 

So, if you really need this then add another ODDR with an inverted D1.

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Visitor
kanwal_
Posts: 6
Registered: ‎05-05-2012
0

Re: problem with ODDR bloc

how to instantiate a ODDR block in my verilog code to remove error 1203 ?,,, plz urgently give me the ans

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: problem with ODDR bloc

Kanwal,

 

1.  Please do not open a new problem or question in an existing thread.  One problem or topic per thread, please.  Instead, you should open a new thread (which you have already done).

 

2.  Please, one post or one thread is sufficient.  You have created 4 posts in these forums with the same request.  This clutters the forums, makes it difficult to see all responses, and adds confusion.  The thread you already created is entirely sufficient.

 

3.  This is a user-to-user forum which is supported by volounteers.  You should not expect immediate responses.  Be patient.

 

4.  Please read the New Users README, which includes both forums use guidelines and some useful information links.

 

-- Bob Elkind

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