Virtex® Family FPGAs

[ilovephysics]

In this particular design, I have a 10 MHz sine wave (from an atomic clock source) as my clock input to my Virtex 5. It's been working pretty well. The sine wave has a 1.4 V peak to peak and is centered around 1.2 V (e.g. it swings from 0.5V to 1.9V). I set the I/O standard for this input to be LVCMOS25. Today when I actually measured the VCCO pin for this bank with a voltmeter, I was very surprised to find out that I have been biasing it with 1.69 V instead of 2.5 V the entire time. 

1. Since my design very much depends on this clock input and it has worked well despite this recently discovered "mistake", does this mean that the I/O bank accepted the incorrect biasing and operated the input pin at LVCMOS18 instead?

2. A follow up question is this: is it true that as long as my sine wave crosses VIH min (voltage-input-high minimum) but doesn't go above VIH max and also crosses VIL max but doesn't go below VIL min, the input buffer will be able to convert it to a square wave clock? Since this sine wave also satisfies these specifications for LVCMOS25 (VIH min = 1.7V, VIL max = 0.7V), I would still be able to use this sine wave signal as my clock if I actually CORRECTLY set the Vcco to 2.5V, right?

3. The reason that it's 1.69 V at the Vcco instead of 2.5 V is that I naively applied the bias by voltage-dividing a 3.3 V with a 100K and a 32K resistors. Before configuration, I do actually get around 2.5 V at the Vcco pin. But after configuration, the Vcco pin draws a lot more current and thus pulls down the voltage level. Now my two solutions are:

a. use lower-valued resistors such as 1k and 320 instead, or 

b. get some voltage regulator, e.g. LDO, to supply the 2.5 V. 

I know b is the safer bet but I want to avoid creating another power plane for 2.5 V since I already got a bunch for 3.3 V and 1.8 V

(just to be clear, I am not actually working directly with a V5 chip but instead designing a daughterboard for an Opal Kelly V5 development board that has expansion connectors for these I/O banks)

[eteam00]

I'll take these questions, one by one, with the understanding that I am not a Xilinx employee with 'inside' knowledge.

1. Since my design very much depends on this clock input and it has worked well despite this recently discovered "mistake", does this mean that the I/O bank accepted the incorrect biasing and operated the input pin at LVCMOS18 instead?

No.  It means you are operating with LVCMOS25 IOSTANDARD (see the datasheet) and a 1.69V VCCO supply -- and you were violating the VIN(max) spec beyond which device reliability and longevity may be degraded.  See DS202 Table 7.

2. A follow up question is this: is it true that as long as my sine wave crosses VIH min (voltage-input-high minimum) but doesn't go above VIH max and also crosses VIL max but doesn't go below VIL min, the input buffer will be able to convert it to a square wave clock?

Not necessarily.  Depending on edge speeds, DC bias, and waveform symmetry, you may see some duty cycle distortion.  You are also greatly susceptible to clock jitter due to the influences of noise combined with very slow (dangerously slow!) edges.  You should consider a clock source with square wave output rather than sinewave.

Since this sine wave also satisfies these specifications for LVCMOS25 (VIH min = 1.7V, VIL max = 0.7V), I would still be able to use this sine wave signal as my clock if I actually CORRECTLY set the Vcco to 2.5V, right?

Yes, subject to the same warnings as above.  This would avoid the violation of the datasheet maximum input voltage.

3. The reason that it's 1.69 V at the Vcco instead of 2.5 V is that I naively applied the bias by voltage-dividing a 3.3 V with a 100K and a 32K resistors. Before configuration, I do actually get around 2.5 V at the Vcco pin. But after configuration, the Vcco pin draws a lot more current and thus pulls down the voltage level. Now my two solutions are:

a. use lower-valued resistors such as 1k and 320 instead, or 

b. get some voltage regulator, e.g. LDO, to supply the 2.5 V. 

I know b is the safer bet but I want to avoid creating another power plane for 2.5 V since I already got a bunch for 3.3 V and 1.8 V

Power plane vs. wide trace routing and voltage divider vs. active regulator are two independent decisions.  The decision for circuit board routing will need to consider DC and peak supply current.  Can you position 0402 or 0201 decoupling caps very close to the VCCO supply pins?

You are the engineer.  It is up to you to do the math and make the tradeoffs.  You can't ask strangers to make these decisions for you, especially without knowing more details than you can pack into a forum thread.

If you don't trust yourself to make the decision, call for help from someone who can help you on-site.

Also, if you look at your VCCO supply with an oscilloscope rather than a voltmeter, you will likely be shocked.

-- Bob Elkind

[ilovephysics]

---

eteam00 wrote:

I'll take these questions, one by one, with the understanding that I am not a Xilinx employee with 'inside' knowledge.

1. Since my design very much depends on this clock input and it has worked well despite this recently discovered "mistake", does this mean that the I/O bank accepted the incorrect biasing and operated the input pin at LVCMOS18 instead?

No.  It means you are operating with LVCMOS25 IOSTANDARD (see the datasheet) and a 1.69V VCCO supply -- and you were violating the VIN(max) spec beyond which device reliability and longevity may be degraded.  See DS202 Table 7.

2. A follow up question is this: is it true that as long as my sine wave crosses VIH min (voltage-input-high minimum) but doesn't go above VIH max and also crosses VIL max but doesn't go below VIL min, the input buffer will be able to convert it to a square wave clock?

Not necessarily.  Depending on edge speeds, DC bias, and waveform symmetry, you may see some duty cycle distortion.  You are also greatly susceptible to clock jitter due to the influences of noise combined with very slow (dangerously slow!) edges.  You should consider a clock source with square wave output rather than sinewave.

Since this sine wave also satisfies these specifications for LVCMOS25 (VIH min = 1.7V, VIL max = 0.7V), I would still be able to use this sine wave signal as my clock if I actually CORRECTLY set the Vcco to 2.5V, right?

Yes, subject to the same warnings as above.  This would avoid the violation of the datasheet maximum input voltage.

3. The reason that it's 1.69 V at the Vcco instead of 2.5 V is that I naively applied the bias by voltage-dividing a 3.3 V with a 100K and a 32K resistors. Before configuration, I do actually get around 2.5 V at the Vcco pin. But after configuration, the Vcco pin draws a lot more current and thus pulls down the voltage level. Now my two solutions are:

a. use lower-valued resistors such as 1k and 320 instead, or 

b. get some voltage regulator, e.g. LDO, to supply the 2.5 V. 

I know b is the safer bet but I want to avoid creating another power plane for 2.5 V since I already got a bunch for 3.3 V and 1.8 V

You are the engineer.  It is up to you to do the math and make the tradeoffs.  You can't ask strangers to make these decisions for you, especially without knowing more details than you can pack into a forum thread.

If you don't trust yourself to make the decision, call for help from someone who can help you on-site.

Also, if you look at your VCCO supply with an oscilloscope rather than a voltmeter, you will likely be shocked.

-- Bob Elkind

---

Bob, thanks again for your help!

      I don't quite understand your answer to my first question. What do you mean by "violating VIN (max)"? Is VIN VIL or VIH?  Can you elaborate on that?

     I have to use this sine wave clock source because all the other equipments in my experiment are synchronized to this clock and my FPGA board is part of this experiment setup. I thought I read somewhere that the input buffer has built in schmit trigger in it?

[eteam00]

I don't quite understand your answer to my first question. What do you mean by "violating VIN (max)"? Is VIN VIL or VIH?  Can you elaborate on that?

• DS202, Table 7.  VIH max for LVCMOS25 is VCCO + 0.3V.
• Your VCCO is (measured by a voltmeter, which is inadequate method) 1.69V.
• Your input logic swing is 1.4V P-P centred about 1.2V, resulting in a VIH of 2.0V.  This is near -- or possibly greater than -- 1.69V + 0.3V = 1.99V.

I have to use this sine wave clock source because all the other equipments in my experiment are synchronized to this clock and my FPGA board is part of this experiment setup.

This doesn't make a 10MHz single-ended sinewave an optimal source clock signal.  Each rising and falling edge is roughly 50nS duration, received by input buffers which are sensitive and gained-up enough to switch in a fraction of a nanosecond. If you are satisfied with performance and reliability, I won't argue with you.

I thought I read somewhere that the input buffer has built in schmitt trigger in it?

• I searched for 'schmitt' and 'hysteresis' in DS202, UG621, and UG190.  No hits.
• Hysteresis implies a low-pass filter.
• You can implement a 2-pin hysteresis solution, using an output pin and a 2-resistor network.
• You can use an off-chip buffer to "square up" the sinewave

-- Bob Elkind

[ilovephysics]

---

eteam00 wrote:

I don't quite understand your answer to my first question. What do you mean by "violating VIN (max)"? Is VIN VIL or VIH?  Can you elaborate on that?

• DS202, Table 7.  VIH max for LVCMOS25 is VCCO + 0.3V.
• Your VCCO is (measured by a voltmeter, which is inadequate method) 1.69V.
• Your input logic swing is 1.4V P-P centred about 1.2V, resulting in a VIH of 2.0V.  This is near -- or possibly greater than -- 1.69V + 0.3V = 1.99V.

How did you get a VIH of 2.0V? I thought VIH = 1.2 + 1.4/2 = 1.2 + 0.7 = 1.9 V, no?

I have to use this sine wave clock source because all the other equipments in my experiment are synchronized to this clock and my FPGA board is part of this experiment setup.

This doesn't make a 10MHz single-ended sinewave an optimal source clock signal.  Each rising and falling edge is roughly 50nS duration, received by input buffers which are sensitive and gained-up enough to switch in a fraction of a nanosecond. If you are satisfied with performance and reliability, I won't argue with you.

I thought I read somewhere that the input buffer has built in schmitt trigger in it?

• I searched for 'schmitt' and 'hysteresis' in DS202, UG621, and UG190.  No hits.
• Hysteresis implies a low-pass filter.
• You can implement a 2-pin hysteresis solution, using an output pin and a 2-resistor network.
• You can use an off-chip buffer to "square up" the sinewave

 About this 2-pin hystersis solution, are you talking about using an op-amp? Basically building a schmitt trigger?

Thanks!

-- Bob Elkind

---

[lamonnis]

You can put a basic OPAMP in comparator mode to have a "numeric" clock... With a trigger you will have  not have a 50% duty cycle if I well remember my courses.

[rcingham]

If it were me I would use a proper comparator IC, running off the same rails as the V5 bank, and carefully select the resistors used to define the pseudo-reference input.

[eteam00]

About this 2-pin hystersis solution, are you talking about using an op-amp? Basically building a schmitt trigger?

Welcome to digital logic design from the 1970s.

slow edge inp signal ---\/\/---+--------->|->FPGA input buffer-----+----> to FPGA logic

                         R1    |    R2    |                        |

                               +---\/\/---|<-FPGA output buffer <--+

The degree of hysteresis depends on the ratio of R1 to R2.  You might try R1=1K, R2=10K to start.

Does this make sense?

-- Bob Elkind

[eteam00]

How did you get a VIH of 2.0V? I thought VIH = 1.2 + 1.4/2 = 1.2 + 0.7 = 1.9 V, no?

I was over-tired and goofy, and instead of dividing 1.4 by 2 and adding to 1.2, I divided 1.2 by 2 and added to 1.4.

My bad.  My math was wrong, but it seemed right at the time.  You are correct.

-- Bob Elkind

[rho88]

Something else to add to this discussion, yes you may be violating the LVCMOS25 specs from table 7 in DS202, however this is not the spec you should be looking at if you are concerned over damaging your device.  It says specifically in table 7 the following:

"Values for VIL and VIH are recommended input voltages."

Table 7 VIH/VIL is for recommended values for different IO standards.  This is not the absolute maximum that a given IO can handle.  The absolute max you would look at VIN from table 1, which will depend on your imput voltage.  So your absolute max would be 2.19 V (if Vcco < 2.5 V).  Additionally, there are power and ground clamp diodes on the V-5 to provide for ESD protection that can help here as well.