05-14-2012 10:35 AM
I am looking for some way to synthesis a GTECH-mapped design (*.ddc, synopsys design compiler netlist format) for Virtex 5 FPGA. (I don't have the RTL code)
Does Xilinx provide any sort of libraries for using with synopsys design compiler (like that is provided by Altera for it's devices)?
If not, How can I change the design format from GTECH library to a reliable *.edif format to synthesis with ISE?
any suggestion is wellcome.
05-14-2012 11:25 PM
Synopsys DC is made for ASICs, not FPGAs.
Ther once was some support for FPGAs, but I don't know how that evolved since some years ago Synopsys DC FPGA was released as a separate product specialized on FPGA design. Check your licenses if you can use that one. It should come with all necessary libraries.
If you take a look at the Xilinx Download page (http://www.xilinx.com/support/download/index.htm) and go for the CAE Vendor Libraries and Synopsys tab selections, you can see that the libraries offered there are for pre V4 Devices and some very old Versions of Synopsys tools.
Rather than using EDIF you should export your design as either a verilog or VHDL Netlist.
Then you could use some clever text filtering program (sed/awk/perl script whatever suits you best) and replace the GTECH elements with their xilinx primitive counterparts (e.g. unisims library).
If done properly and no strange macros are in the design, ISE should be able to synthesize this.
Quite some work to do, but the only solution I can suggest.
Have a nice synthesis