Virtex® Family FPGAs

[yangqiang_jx]

My messge posted yesterday disappeared for whatever reason. So I have to ask the question again.

Does virtex5/6 PCIe Core support concurrent bi-directional PCIe bus-master DMA?

Page 8 of XAPP1052 under the section of 'Initiator Logic' says "the bus master design only supports generating one type of a data flow at a single time". Jungo's windriver sample 'bmd_design' also verifies that, in a single transaction, either upstream or downstream can be executed, even if the DMA option is set with DMA_TO_FROM_DEVICE.

Is there any way we can configure virtex5/6 PCIe Core to do concurrent bi-directional PCIe bus-master DMA?

Many thanks in advance.

Q.Y.

[mcgett]

Your prior post was moved to the correct forum:

http://forums.xilinx.com/t5/PCI-Express/virtex-5-6-duplex-bus-master-DMA/m-p/241040

[yangqiang_jx]

Thank you.