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Xilinx ships first 20nm Virtex UltraScale FPGA – Why this matters to you

by Xilinx Employee ‎05-13-2014 10:21 AM - edited ‎05-13-2014 03:55 PM (2,165 Views)

Xilinx announced today that it has shipped the first 20nm Virtex UltraScale FPGAs—XCVU095 devices. These are the same devices that taped out in January. (See “20nm news: Virtex UltraScale tapes out... and 12 more things you might not know about UltraScale.”)

 

 

 20nm Virtex UltraScale VU095.jpg

 

 

Virtex UltraScale XCVU095 All Programmable Device.jpgThis shipment of the first 20nm Virtex UltraScale FPGAs follows first shipments of 20nm Kintex UltraScale devices by about six months and you might well ask “What are the differences between the high-end 20nm Virtex UltraScale and mid-grade 20nm Kintex UltraScale FPGAs?”

 

Both device families share the UltraScale Architecture which includes many routability improvements, now baked into the latest release of the co-developed Vivado Design Suite. Sure, there are capacity differences between the 20nm Virtex UltraScale and Kintex UltraScale devices, but both 20nm UltraScale device families are based on many of the same basic building blocks including logic cells, block rams, DSP slices (the UltraScale Architecture’s new and improved DSP48E2, see “The UltraScale DSP48E2: More DSP in every slice”).

 

Both device families also incorporate 16Gbps GTH SerDes transceivers.

 

Many of these shared building blocks were proven in silicon when the first Kintex UltraScale devices shipped last year. With the recent shipment of Virtex UltraScale devices, three more major 20nm building blocks have now been proven:

 

  1. The 32.75Gbps GTY SerDes transceiver (more on that in the next blog post!)
  2. The 100G Ethernet MAC hardened IP core
  3. The 150Gbps Interlaken hardened IP core

 

The 20nm GTY SerDes transceiver can drive 32.75Gbps bidirectionally chip-to-chip—which is especially handy for driving 100Gbps plug-in optics used in data-center networks and for other 4-lane, 100Gbps CAUI-4 networking equipment designs. These applications can also put the hardened 100G Ethernet MAC to good use. In addition, the 20nm GTY SerDes transceivers can directly interface with the latest breed of high-speed chips like the MoSys 3rd-generation Bandwidth Engine at maximum speed. (See “3rd-Generation Bandwidth Engine from MoSys (Bigger, Better, Faster) needs sixteen 28Gbps lanes to strut its stuff.”)  

 

The 20nm GTY SerDes transceivers can also drive 28.21Gbps bidirectionally over a backplane, which matches up nicely with the hardened 150Gbps Interlaken core. Interlaken is increasingly popular as a high-speed backplane interconnect used widely in networking equipment. (For example, see “Huawei and Xilinx unveil prototype 400GE Core Router at OFC 2104. FPGAs do the heavy lifting.”)

 

These three new 20nm Virtex UltraScale blocks, now proven in silicon, enable single-chip implementation of 400G and 500G systems.

About the Author
  • Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.