Xilinx Boards and Kits

[fvdalcin]

I started to use the DVI video output device Chrontel CH7301C on ML505 board recently, and I've been experiencing some problems.
My prior objective consists in generating a test pattern video in order to verify my design.
In an effort to do that, I'm using an I2C master controller, which I’ve downloaded from opencores.org, to configure the Chrontel CH7301C device's registers via I2C.
I'm quite sure I'm writing correctly, since after the write burst, I can read the values I've written previously.
However, I can't be a hundred per cent sure, since the device doesn't generate the test pattern.
So, here are the most probable places I think the problem may be:

1- The I2C master core is not working properly
2- I'm not configuring the device correctly
3- The device requires some extra signals which I'm not providing with
4- The device or the monitor is not working properly

Here are my arguments, explaining what I've done in my design, regarding to the topics mentioned above:

1- My SCL and SDA signals are connected to the U27 & T29 pins per the ML505 User's Guide document (UG347 page 51).
I can read the register's default options via I2C. Therefore, my controller is able to read correctly.
So, as I explained before, I perform a write cycle followed by a read cycle, which shows that I've read
the same value I've written. So, I'm quite sure it's working properly.

2- Here are the values I'm using as reference to configure the device's registers.
             /* ( RAB, DATA, DEV_ADDR   ) */
   write_iic_dvi(0x1C, 0x00, CH7301_addr);     //0x00 1x pixel frequency and non-inverted XCLK
                                                                  //0x01 2x pixel frequency
                                                                  //0x04 Inverts XCLK
                                                                  //0x05 2x inverted XCLK
                                           
   write_iic_dvi(0x1D, 0x48, CH7301_addr);     //0x48 is default
     
   write_iic_dvi(0x1F, 0x9C, CH7301_addr);     //0x9C IDF=4 with active high VSYNC and HSYNC
                                                                  //0x84 IDF=4 with active low VSYNC and HSYNC
                                         
   write_iic_dvi(0x21, 0x0D, CH7301_addr);     //0x0C Enables VSYNC and HSYNC output data for IDF=4
                                                                  //0x0D Enables VSYNC, HSYNC, and RGB output for IDF=4
                                                                  //0x04 Disables VSYNC, HSYNC, and RGB output for IDF=4


   write_iic_dvi(0x33, 0x06, CH7301_addr);     //0x08 for frequencies <= 65MHz  //0x06 for f > 65MHz
   write_iic_dvi(0x34, 0x26, CH7301_addr);     //0x16 for frequencies <= 65MHz  //0x26 for f > 65MHz
   write_iic_dvi(0x36, 0xA0, CH7301_addr);     //0x60 for frequencies <= 65MHz  //0xA0 for f > 65MHz                                           
   write_iic_dvi(0x48, 0x19, CH7301_addr);     //0x18 No test pattern - input data is used
                                                                  //0x19 Color Bars test pattern output
                                                                  //0x1A Horizontal Luminance Ramp test pattern output
                                           
   write_iic_dvi(0x49, 0xC0, CH7301_addr);     //0x01 All circuitry is powered down
                                                                  //0xC0 DVI is in normal power function
                                           
   write_iic_dvi(0x56, 0x01, CH7301_addr);     //0x00 Disable YCrCb to RGB conversion
                                                                  //0x01 Enable YCrCb to RGB conversion

Those values were suggested by the user called mmcshmi11, in the following post:
http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Can-t-talk-to-Chrontel-CH7301C-on-ML505-Video-I2C...

3- Those are the signals I'm providing the device with. Maybe here I'm screwing something up.
DVI_D (11 downto 0) <= (others => '1');
DVI_DE                   <= '0';
DVI_GPIO1              <= '0';
DVI_H                     <= '0';
DVI_RESET_B        <= not rst;        --rst signal is an asynchronous active high reset
DVI_V                     <= '0';
DVI_XCLK_N           <= not clk;        --clk signal is the USER_CLK, which is locked to the AH15 pin on ML505 and has a frequency value of 100 MHz
DVI_XCLK_P             <= clk;

I assume that, if the device is in the test pattern generation mode, I don't need to provide it with video signal neither with sync signals, since it is supposed to do that by itself.

4- The device and the monitor are working, because I can run the slide-show example provided by Xilinx in the flashcard that comes with the board.

Can anyone see where I'm possibly doing something wrong?

Thanks

Felipe

[eteam00]

Felipe,

The scope of your "problem" is way way too broad for me to spend the required time for review and reverse engineering.  My specific suggestion for you is this:

• reload the base DVI design (which you said is working)
• make small changes from the base design, one at a time, and check/debug the results at each iteration.

By making small, individual changes, the scope of where to look for new problems is (by definition) very narrow.  If you have a working base design and a broad sweeping redesign to implement, this is the surest path to a succesful conclusion (i.e. make and debug small changes, one at a time).

- Bob Elkind

[gszakacs]

I don't see anything in the Chrontel Data Sheet that indicates that it will generate a test pattern

without active sync and DE signals on its input pins.  It would require some sort of timing generator

to do that and there is no mention of timing parameters (line and frame size) for the test pattern.  It

just looks like the test pattern replaces the input data.

-- Gabor

[fvdalcin]

I appreciate your hints Bob.
I have no doubts that your method is the most correct to implement a FPGA design. However, I don't have the code of the example design; therefore I'm not able to take something that is already working as example and build my design using it as reference.
Xilinx provides just the bitstream of the slide-show example, so I'm not able to use it as reference.
I tried to test and validate each module separately, but when it comes to integration, I have no alternative but to put things together.
However, I think my problem is in the I2C controller. I will use Chipscope to assure I'm configuring the DVI device correctly.

Thanks for your help,
Felipe Dalcin

[fvdalcin]

You are right Gabor,

I've assumed the DVI device would generate the sync signals by itself, however the data sheet says only that when the test pattern mode is on, the device will ignore the data input and use its own test pattern inputs.
I'll develop the design that generates the sync signals and see what happens.
And I still think my I2C core is not sending that correctly. I’ll scope sda and scl signals and see what’s going on.

Thanks for your help,
Felipe Dalcin

[eteam00 · Accepted solution]

Felipe,

My mistake, I assumed that a development board would provide a license for all IP with source code.

With Chrontel device, you will certainly need a functioning I2C interface.

I might actually have a useful suggestion for you...  With a digital video interface, if you're close to correct formatting but still not 100% correct, often a digital interface will still be completely non-functional and indecipherable.  With an analogue interface, you can discern quite a bit with an oscilloscope.  The Chrontel part can output analogue VGA as well as purely digital DVI.  You can use the analogue output to give you more intuitive information about signal levels, coding, and timing.

Good luck to you.  It sounds like you know what you're doing.

- Bob Elkind

[fvdalcin]

I've written in the CH7301C registers in order to have an analogue output, however it seems like the device is powered down, even after I've written in the register to power it up.

I’ve used an oscilloscope to scope the Xilinx’s example, and then I could see the sync signals perfectly. But when I load my design, the device’s outputs drive no signals.

Does someone have a working example of which values to choose and to configure the device?

I am probably forgetting something, which is causing me all the trouble. I'm quite sure the problem is in the device’s configuration.

Thanks,

Felipe Dalcin

[gszakacs]

If you can read back the registers from the Chrontel part, then you can at least make

sure that you wrote them correctly.  If not, you can compare the I2C bus traffic from

the working Xilinx design to the traffic from your design.  This would be easier with

a logic analyser.  If you don't have one, there are some very inexpensive I2C bus

analyzers available that plug into a PC's USB port and allow you to monitor the

I2C traffic very easily.  That would also allow you to run the Xilinx code and see the

values that are being written to the Chrontel part.

I'm not sure if that part resets everything when you re-load the FPGA, but if not,

then you could run the Xilinx application and follow that with your code without

powering down the system.  If you can get something to work that way, it would

point to some register you aren't setting at all.  If it doesn't help then you're more

likely setting something wrong.

HTH,

Gabor

[eteam00]

Two suggestions, in case you haven't already considered them:

1.  You can always check with the Chrontel support folks on recommended register settings.  They should be the experts for this device.

2.  Be wary that you may actually be setting the Chrontel registers correctly, but your settings may be over-written by some routine other than the start-up init routine.  (note: this is pure speculation on my part, nothing more).

Gabor's suggestion is an excellent idea -- append your register setting code to the baseline (working) Xilinx reference code. 

If your appended code results in the Chrontel device shutting down, then:

• comment out your code and re-confirm that the part still stays "alive"
• un-comment out your code, selectively and in bits or chunks, until you've chased down the specific settings or lines of code which result in Chrontel shut-down.  Divide and conquer.

- Bob Elkind

[fvdalcin]

Hello,

I’m glad to tell you my problem is almost solved. I was sure my I2C interface was working and now I confirmed it.

Finally I’ve got some video info from the outputs of the DVI interface of ML505 board, which made me very happy.

Here is the configuration I'm using:

Register addr (hex)                        Register name                  Configuration data (hex)

49                                                          PM                                        C0

21                                                          DC                                         09

33                                                          TPCP                                     08

34                                                          TPD                                       16

36                                                          TPF                                        60

I’ve found this configuration data in the following Xilinx documentation:

XPS Thin Film Transistor (TFT) Controller (v2.00a)

This documentation also contains the timing diagram for the DVI sync signals, which revealed to be very useful to me.

I used Bob’s hints also, and tried to work with analogue video. However, all the monitors I have in the lab have only the DVI-D input. So, I used the DVI-D to VGA converter that comes with the board, to use the VGA input of the monitor. This was an amazing hint, since I was quite near the solution, but the monitor still doesn’t get a perfect digital signal.

Then I tested the test pattern generation, which worked just nice.

I still have a blinking screen, which reveals I have some sync problems, but that’s nothing I can’t handle myself.

I appreciate the help I received here,

It was essential to get to the right solution

Thanks again,

Felipe Dalcin