Xilinx Boards and Kits

[vikxxxx]

Hi,

I faced this problem before. In ML505 board, the pin AM9 is connected to the reset pin of the Chrontel chip. You need to drive this pin to 0 in your design.

If you are using EDK, add the following line to your .mhs file
PORT vga_reset_pin = sys_rst_s, DIR = O

Add these lines into your .ucf file
Net vga_reset_pin LOC = AM9;

Net vga_reset_pin IOSTANDARD = LVCMOS33;

NET vga_reset_pin TIG;

[david.greaves]

The earlier posting enabled DVI output (I think).  The following does VGA mode.

I fiddled around with various settings until the following worked for me.  This generates VGA output for data or built-in test patterns on the ML605 card.

        static void Main()
        {
            I2C_master.i2c_chrontel_cmd(0x49, 0xC0); // DVI Off, VGA ON.                            
            I2C_master.i2c_chrontel_cmd(0x21, 0x09); // Enable H synch output + 1                   
            I2C_master.i2c_chrontel_cmd(0x22, 0x16); // Enable V synch output                       
            while(true)
            {
               while(!checker)  Kiwi.Pause(); // nb: not debounced: so a bit weak!                  
               I2C_master.i2c_chrontel_cmd(0x48, 16+8+1);
               while(checker)  Kiwi.Pause();
               while(!checker)  Kiwi.Pause();
               I2C_master.i2c_chrontel_cmd(0x48, 16+8+2);
           while(checker)  Kiwi.Pause();
               while(!checker)  Kiwi.Pause();
               I2C_master.i2c_chrontel_cmd(0x48, 16+8+0); // Normal operation again.                
           while(checker)  Kiwi.Pause();
            }
    }

I attach the source code in C# for our Kiwi compiler and also the generated verilog subsystem.

[I realise you wont want to use Kiwi but the C# is very readable!]

David Greaves