02-15-2009 12:24 PM
I've recently purchased the S3E Starter kit, and I've got some questions.
First, I've got a little hobby project that needs to read in 50-60K of ~250ns wide negative-going 5v pulses, and store the absolute starting time of each pulse. Time would start with the falling edge of the first pulse, and would stop after ~203ms. The time/distance between the pulses define the data desired, but high resolution isn't terribly important because there are only three possibilities: 4us, 6us, and 8us. The time between pulses might be slightly shorter, and almost never longer(which would be an error condition)
Once these times are recorded in memory, they need to be transferred to a PC at a decent speed, hopefully at a couple mbps+.
I plan on using the onboard 32MB DDR SDRAM to store these times, and then the USB connection to transfer data to the PC.
Can anyone please give me some overall design advice? I've chosen to use Verilog, and I'm already about half way through "Learning FPGAs by Example: Verilog"
I guess that using the MIG to generate the DDR controller is the best method. I've downloaded, installed, and ran the generator --- but now I'm sort of at a loss of how to use what MIG's created. Inside the example_design folder, there is an rtl folder that contains the verilog source. But there are something like (34) different source files. And some of them are quite large. I imagined a single monolithic .v I'd include in my project, and then a simple interface of "read byte at address x" or "write byte at address y." Is this not realistic? I've read through the User Guide for the MIG, but I can't find anyplace that talks about actually USING the code that's generated.
Can I use the USB port for data transfer, not just programming? Are there code examples or pre-done modules that I could plug-in?
My high-level idea now is to do something like:
have an always block that reacts to the clock, and creates a counter. Use the built-in 50mhz clock, and a 26-bit counter which gives me a room for 1 integer per tick. 2^26 ~= 67million. Once we get to ~203ms, then stop counting, and start the transfer to the PC.
have an always block that reacts to the incoming data. If it sees a falling edge, write the current counter value to the first memory location, advance memory location counter.
I guess this is sort of a logic analyzer type of application, but the rising edge doesn't really need sampled. I guess just for niftyness-sake(is this a word?), it would be cool to store the rising edge time too.
I'd appreciate any advice. Of course I'll take recommendations for better Verilog books, or any related reading material.
P.S. I'm a hobbyist with no formal electronics training but experience with microcontrollers, and several programming languages.