05-28-2012 10:46 PM
Hi, I am having the verilog code for AES-128. I am using ISE 10.1 and by using it I can successfully synthesize the code and can also generate the .bit file to download on the FPGA, but I cannot simulate the code. Can someone help me in this regard? I will be very grateful. Thank you.
Solved! Go to Solution.
05-29-2012 04:07 PM
Which code? Have you asked the author of the code for help? Do you understand how the code works and how to use ISim or ModelSim and test benches?