04-23-2012 08:34 AM
I intented to learn how to use the TEMAC core t, so I used CoreGenerator to build a TEMAC Warpper core and planned to run the example design which provided by the CoreGenerator on the ML507 , which can achieve a function of swapping SA and DA of the frame sent by PC .But it doesn't work.
I did it as these two guide :
I think I did every steps in these guide , but after I downloaded the .bit file to the ML507 , I run cmd command on windows xp , and ping the ML507 as the first guide discribed , but there is only RX led blinked when I ping the board , the TX red show nothing , then I use Wireshark to watch the frames and there is noly the IGMP I sent was captured , the FPGA relay nothing .
I run a design with ll_temac core in XPS on the same board and it work well , I can ping the borad form my PC ,so I think there should be no physical damage in the hardware of the platform ,may be I need to do other configuration ,such as the Switch or the Jumper . Though I set the Switch as the XAPP957 discribed , you guys also can give me some advises ,maybe I miss something important .
then , I found the doucument on the Xilinx website
I did some debug as it suggest , and I found something .
1. the signal RESETDONE_0 is "1" , I think it mean that the ilitializing of GTX and the CLK is OK
2. First , I found the rx_ll_data_out in the client_side_FIFO_emac0 was recieve nothing ,then I found that the CLIENTRXDVLD is alway "0" and the CLIENTRXFRAMEDROP is alway "1" , I trun the function address filter off , and it was strange that even I didn't connected the Ethernet cable to the ML507 ,the CLIENTRXFRAMEDROP is still ''1" , so I guess there may be something wrong in the lower level .
3. I captured some signal from the GTP ,then I found there is alway some singals received from the GTX port RXDATA0 and the singal RXELECIDLE0 is alway "0" (so the signal SIGNALDET in TEMAC is alway "1") no matter I connected the ethernet cable or not , it's so queer！！does it mean that the Marvell 88E1111 send signals to GTX continuously ，is this proformance normal??
above all is all I did to the board now , could anyone tell me what I sould do next or help me analysis it ...I planned to attach my design ,but my network condition is worst ,....I can do this now, I'll try tomorrow .
by the way ,me ISE version is 10.1 ,the version of the TEMAC warpper core is 1.5
thank you all , I really need help ~ waiting online ~~
Solved! Go to Solution.
04-25-2012 02:07 PM
I'd recommend checking that Synchronization (EMAC#PHYSYNCACQSTATUS) and AN have completed for the SGMII link. If so is the MAC set to the correct Auto Negotiated speed?
04-25-2012 09:36 PM
thanks for reply~~
I have checked the PHYSYNCACQSTATUS ,it's always asserted high dispite the connection of ethernet cable , It seems that the Marvell 88E1111 sent signal to the GTX continuously , no matter I connect the ehthernet cable to the RJ45 or not , is that normal??
and the setting for AN speed is :
-- Configure the MAC operating mode
-- MDIO is enabled
constant EMAC0_MDIO_ENABLE : boolean := TRUE;
-- Speed is defaulted to 1000Mb/s
constant EMAC0_SPEED_LSB : boolean := FALSE;
constant EMAC0_SPEED_MSB : boolean := TRUE;
constant EMAC0_USECLKEN : boolean := FALSE;
constant EMAC0_BYTEPHY : boolean := FALSE;
I think it is configuration of 1Gbps ,and when I connected the ML507 and my PC , the connecting information on my my is 1Gbps , too
and ,I noticed that
-- MDIO is enabled
constant EMAC0_MDIO_ENABLE : boolean := TRUE;
this code is provided by the CoreGenerator ,but I set the "MDIO enable " box unchecked in the GUI ,why here is set to TRUE , there is no any MDIO or MDC interface in my TOP level , is that normal ?
could you please run my design on your ML507 ,if you have one ...I think I do everything need to do ,but it doesn't work
04-27-2012 12:35 AM
I do some test again ,and I found something maybe abnormal...
Yestoday I said the EMAC#PHYSYNCACQSTATUS is alway assert high after resetting , however , today I found that's not .
I said that yestoday because I connect this signal to a LED on the board , since I can't find this signal in the Chipscope CDC setting , and I saw the LED alway light , so I think it's always HIGH . I made a fatal mistake with that , there is a possibility that the signal is low and the LED was off in a very short time which I can't notice with my eyes .
so ,today ,I add this code to my design ,and I can found the singal EMAC0CLIENTSYNCACQSTATUS in my CDC setting
attribute keep : string;
attribute keep of EMAC0CLIENTSYNCACQSTATUS : signal is "true";
and I found the signal EMAC0CLIENTSYNCACQSTATUS was not always assertd high after resetting ,actually , almost every time I captuer the sample (I did this random and without ethernet cable connceting ) there was a period(very short ) this signal was low , I do a Screenshot and I attached the image :
does this mean that the auto-negotiation between the FPGA and Marvell 88E1111 via SGMII is unstable?? or that's the reason why I can't receive the frame sent from my PC??
04-30-2012 11:16 AM
Hi, is EMAC#PHYSYNCACQSTATUS constantly toggling or was it just low imediately after a reset? You can try doing several triggers on PHYSYNCACQSTATUS going low. It it is constantly toggling then this would result in AN never completing and thus not be able to recieve/transmit frames. Synchronization maybe lost if you are recieving invalid data (disparity errors or not in table errors) or if signal detect is going low.
The AR43330 that you pointed to earlier has some addtional debug suggestions for specific GT signals to look at: http://www.xilinx.com/Attachment/Xilinx_Answer_433
If you are still encountering issues, I'd recommend opening up a support case to debug further.
05-02-2012 01:43 AM
thank you ,
the EMAC#PHYSYNCACQSTATUS is constantly toggling ...I set a low triggers on PHYSYNCACQSTATUS ,and it constantly be triggered .....not only just happened after a reset . I think it means that the AN never completing ,or it had been completed but soon breakdown then the AN must be recompleted ,and then breakdown......never ended ..crazy...
you said"Synchronization maybe lost if you are recieving invalid data (disparity errors or not in table errors) or if signal detect is going low. "
and I did some checking , I didn't connceting the ethernet cable to the rj45..so I think there should be no any data except the AN need singal sent by the Marvell 88E1111, and I use Chipscoupe to observe the signal_detect signal , it never went low ....so I think it's not the matter.
The key problem now I think is that why the AN never completed ,and what caused the AN unstable...I can run a Lwip_demo in XPS successfully so I think the board is ok ..
I used Chipscope to capture the signals RX_DATA0 and TXDATA0
I found when the EMAC#PHYSYNCACQSTATUS is high ,the TXDATA0 is repetively sent "BC B5 00 00 BC 42 00 00"
and the RXDATA is repetively recieved "BC B5 01 00 BC 42 01 00" I looked up the 802.3 -2005 , I knew that it is /C/ Ordered_set , but I am not very familar with the 802.3 , I guess should the RXDATA and TXDATA be the same ?
and when the EMAC#PHYSYNCACQSTATUS is low ,the TXDATA is the same as usual ..but the RXDATA is totally mess
05-02-2012 03:03 PM
05-02-2012 06:44 PM
i don't know how to express my gratitude ,it's realy help me a lot ....It's stable now ,I think it's ok ,but unfortunatly ...the RJ45 on the ML507 is broken , anyway ...the EMAC#PHYSYNCACQSTATUS never go low ...I think it's working now ...
thanks again ...If somebody want to discuss TEMAC with me ...send me email firstname.lastname@example.org