03-30-2009 08:44 PM - edited 03-30-2009 08:45 PM
Thanks for the reply!
I got the PHY to auto negotiate. It was a bad jumper on the board (who would of figured :o ). I am still unable to get the loopback example working. I see the RX light blink when I send a frame. However, the TX light never blinks. It is possible the elements driving the TX is improperly connected, or a timing contraint is not met.
Any guidance would be appreciated! I attached a file with the project.
04-12-2009 02:25 AM
I am also trying to implement the "ethernet example design", actually on a ML507 board (Virtex-5 FXT, XC5VFX70T-1136-1) but had no luck with succeeding.
The PHY obviously auto negotiates, since I have connected the ML507 board to my computer's gigabit ethernet NIC and while operating the LEDs "UP" and "1000" light.
When I try to ping some address (after disabling every other PC's NIC) the RX LED on the ML507 board lights, but there is no response as expected from the address-swap module and the TX LED does not blink at all. Wireshark confirms there was no response from ML507.
I have tryed both GMII and SGMII and decided to try to run it with SGMII since the board generates the 125MHz clock for SGMII when properly set with the dipswitch at the bottom and also because if one day I will need to route my own board there will be less work with SGMII.
However, first I need to get the address-swap module to work and currently I ran out of ideas. I have noticed that the example design's UCF file does not describe the TXN,TXP,RXN and RXP connections. If I try to set them manually as follows:
#INST "eth_TXP_0" LOC = "M2";
#INST "eth_TXN_0" LOC = "N2";
#INST "eth_RXP_0" LOC = "N1";
#INST "eth_RXN_0" LOC = "P1";
then the PAR can not successfully route the design but without those instantiations I am not sure how the design should work, since it would not be specified where the TX and RX pairs get connected and routed.
The ones that did succeed with the example design, did you specify any other constraints? I tryed to help myself with this guide:http://www.xilinx.com/products/boards/ml505/docs/m
Since I am not an experienced FPGA designer, any help would be appreciated.
Thank you and Best regards,
04-12-2009 07:07 PM
I was looking at my HDL it may be the manner the GTX clock is generated. This a code snippet from how my clock is generated:
-- Generate 125MHz (gtx_clk) and 200MHz (ref_clk)
clk125_dcm : DCM_BASE
generic map (
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5)
(CLKIN => clk,
CLK0 => clk_fb_emac1,
CLK180 => open,
CLK270 => open,
CLK2X => ref_clk_bufg,
CLK2X180 => open,
CLK90 => open,
CLKDV => open,
CLKFX => gtx_clk_1_i,
CLKFX180 => open,
LOCKED => dcm_locked,
CLKFB => clk100_emac1,
RST => rst);
fb_bufg : BUFG port map (I => clk_fb_emac1, O => clk100_emac1);
gtx_clk_bufg : BUFG port map (I => gtx_clk_1_i, O => gtx_clk);
refclk_bufg : BUFG port map (I => ref_clk_bufg, O => ref_clk);
It is derived from the 100MHz DIP Switch Settings for Super Clock Generator (SW6)
1 (N0) OFF
2 (N1) OFF
3 (N2) ON
4 (M0) ON
5 (M1) ON
6 (M2) OFF
7 (SEL1) ON
8 (SEL0) OFF
04-12-2009 07:58 PM
what is the difference between:
1)NET PHY_TXC_GTXCLK LOC="J16"; # Bank 3, Vcco=2.5V, No DCI
2)NET PHY_TXCLK LOC="K17"; # Bank 3, Vcco=2.5V, No DCI
04-13-2009 09:09 AM
I believe that GTXCLK is the clock the designer needs to supply to the TEMAC core, while the TXCLK and RXCLK are clocks generated by the PHY. Someone please correct me if I'm wrong.
As for my project I have successfully implemented and tested the TEMAC core into my design and am now able to receive and send data over Ethernet.
However, there are still two things that concern me:
1.) Why can the Client interface be just 8-bit wide using all the interfaces but Ethernet-1000X? I am using SGMII, so I am stuck 8 bits of data width.
2.) Occasionally my design's transmitter starts flooding the network with strange data; WireShark detects it as:
MAC SRC: aa:bb:cc:dd:ee:ff
MAC DEST: 01:80:c2:00:00:01
This occurs always when trying to implement a PLL-ADV structure (I need some custom clocks) and also randomly (I do not know the cause yet). Maybe anyone recognizes the problem and could provide me a hint?
Thank you and best regards,
04-13-2009 09:25 AM
The GTXCLK pin is it an input? What does that pin connect to on the FPGA? The TXCLK would obliviously connect to the PHY TXCLK pin. Correct?
Have you tried simulating your design? It looks like MAC control packet to me.
04-13-2009 09:41 AM
Try looking at the schematics for the 125MHz clock from the "Super Clock Generator" IC... or maybe using a PLL to generate a 125MHz clock from 100MHz (that will be less accurate, however).
MAC control packet? Huh, why do you think does it get produced anyway?
04-13-2009 10:42 AM
You may have Flow control Enabled on your design.
I generated a 125 Mhz and a 200 Mhz with a DCM fead 100Mhz.
Can you show me your design? I am having some difficulty with the FPGA sending back information. I have a feeling it has to do with the TX clock.
04-13-2009 11:00 AM
My design uses SGMII and is based on this guide:
The constraints that may concern you are:
INST "MGTCLK_N" LOC = "P3";
INST "MGTCLK_P" LOC = "P4";
NET "PHY_RESET_0" LOC = J14; # ML505 PHY Reset
Hope this helps,