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Visitor
moiseev
Posts: 6
Registered: ‎03-06-2012
0
Accepted Solution

ML605, Base Reference Design. Again.

Greetings, everyone.

I've been struggling with Base Reference Design (BRD) for a month now and, as it seems, have tried everything, but still with no result.

I'm trying to connect to ML605 but BRD is "Not connected to FPGA". I've restored board flash content and the CF card. Before that i've experienced red "system error" LED after pressing SW3, now it's glowing pure green so that problem was settled. I've tried installing different versions of WinPcap (current v.4.1.2 and default v.4.0.2), i've tried setting up IP-address in my ethernet adapter to 192.168.1.100 (subnet mask - 255.255.255.0 and default gateway - 192.168.1.1 as someone suggested, also tried that without setting gateway) but all in vain. I'm using Windows XP (SP3), so it's supposed to work, but it isn't. I've installed WireShark and when I start BRD application WireShark shows me a bunch of "malformed packets" going out to the ML605 (if needed, I could attach the *.pcap file) with mentioned earlier "Not connected to FPGA" message in BRD.

To state it clear, I have read almost every topic in this forum which included words "ML605" and "Base Reference Design", have tried #AR33229 and other recommendations in other topics, so I'm realy desperate and don't know what to do.  Please, help.

Xilinx Employee
tmcdowe
Posts: 165
Registered: ‎12-17-2007
0

Re: ML605, Base Reference Design. Again.

Are you using Windows XP on real hardware or in a virtual machine?

 

Also, the malformed packets may be a red herring -- the BRD uses raw Ethernet frames to talk to the board so WireShark may be getting confused because it's expecting TCP/IP packets.

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Visitor
moiseev
Posts: 6
Registered: ‎03-06-2012
0

Re: ML605, Base Reference Design. Again.

>Are you using Windows XP on real hardware

Yes, real hardware.

 

>WireShark may be getting confused

Oh, so everything may be working correct? But still, BRD shows "Not connected to FPGA".

Xilinx Employee
tmcdowe
Posts: 165
Registered: ‎12-17-2007
0

Re: ML605, Base Reference Design. Again.

On my second point, I wasn't trying to say that that BRD is "working" -- obviously it's not since you don't see it connect to the FPGA. What I was trying to indicate was that WireShark's sniffing may not be a good indicator of "failure" since WireShark would be expecting something other than what the BRD uses.
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Visitor
moiseev
Posts: 6
Registered: ‎03-06-2012
0

Re: ML605, Base Reference Design. Again.

>WireShark's sniffing may not be a good indicator of "failure" 

OK, got the point. So, what should i use instead? And, more important, what to do at all?

Also, should the board be inserted in PCIe port while running BRD or is supposed to be powered by adapter and stand alone? I can't figure it out from UG533 unambiguously.

Xilinx Employee
tmcdowe
Posts: 165
Registered: ‎12-17-2007
0

Re: ML605, Base Reference Design. Again.

No, it doesn't need to be in a PCIe slot -- I've run the BRD many times with the board just sitting on my bench.

 

WireShark is fine for looking for traffic (which it looks like you're seeing) -- just don't get concerned with the malformed packets part.

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Visitor
moiseev
Posts: 6
Registered: ‎03-06-2012
0

Re: ML605, Base Reference Design. Again.

I've decided to run BIST once again and noticed this:

 

Reading SRECORDS from Compact Flash file bist\6.rec:

120970 bytes read from file. SRECORDS at: 0x50100000
Bootloader: Processed (0x)000009c4 S-records
Executing program starting at address: 00000000

********************************************************
********************************************************
**     ML605 - Temac Test                             **
********************************************************
********************************************************
Setting Temac and DMA

Warning: This example could take minutes to complete without I-cache enabled
Transmitted Packet!

Received Packet!

 

The warning I get is not supposed to be there, I guess. But I haven't seen it before. All the jumpers and switches are set according to XTP056. What is the cause of it?

Visitor
moiseev
Posts: 6
Registered: ‎03-06-2012
0

Re: ML605, Base Reference Design. Again.

Greetings again.

Regardless of the error mentioned above, I've decided to try running XAPP1144 and it all went well. So, I guess it must be something in the BRD, 'cause the board work fine, transmits and receives packets via ethernet.

Anyway, thank you, 

Visitor
kirick
Posts: 3
Registered: ‎03-10-2008
0

Re: ML605, Base Reference Design. Again.

I think the issue with the Base Reference Design Interface is with regards to the version of WinPcap that is being used.  The version of WinPcap that is installed with the included .msi is 4.0.1 which works fine for Windows XP.  However, if you have installed the latest WinPcap (v4.1.1 and above) either manually or through WireShark installation the base design software stops working.  My guess is the API interface to WinPcap has remained the same but has different functionality in the newer versions.  I have tested several ML605 boards on Windows XP using versions 4.0.1 (included with msi) and 4.1.2 (latest available).  My experiments show that WinPcap v4.0.1 is the only one that works with the reference software. 

 

For us Windows 7 users, we are out of luck as WinPcap 4.0.1 does not install on Windows 7.   One option is to use something like Packet.net and fire off Ethernet packets directly.

 

If you working on Windows XP then you are in luck.  Just uninstall the existing WinPcap from your system (assuming its version 4.1.1 or greater) and then rerun the .msi and accept the WinPcap install option.

 

Good luck!

Visitor
rhearty1
Posts: 12
Registered: ‎02-15-2012
0

Re: ML605, Base Reference Design. Again.

Nobody answered his question about the warning message:

 

"Warning: This example could take minutes to complete without I-cache enabled"

 

Xilinx, can you offer something here? I am seeing the same issue.