Xilinx Boards and Kits

[venkat_vs2k2]

Hi , 

I am trying to use the LCD display of ML605 board by using my VHDL code to initialize and control it . I have seen other forums and posts. I have also referred to the Spartarn 3 Guide timing for the board.  I used few references and made up my controller for the LCD.

But i see that whenever i send 8 bits of data to write to the LCD ,, the upper 4 bits are being sent properly, but the lower 4 bits are always stuck at "1111" , Hence i always get the display characters corresponding to the last ROW in the CG ROM corresponding to the upper 4 bits that i send..

I m not sure if i am missing out something.or if i m not initializing the LCD properly.

Could someone point me to the mistake i m making ?

Thanks, 

Venkat.

[bwiec]

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 i see that whenever i send 8 bits of data to write to the LCD ,, the upper 4 bits are being sent properly, but the lower 4 bits are always stuck at "1111"

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How are you seeing this? Sim or Hardware?

Side note: I see a lot of if, elsif statements without an else. This is typically not recommended and will usually result in latches. Also, you have a lot of signals assigned in one condition of if-elsif and not in other conditions. Again, not recommended and results in inferred latches. Consider using default assignments (or assign every signal in all states).

[venkat_vs2k2]

Hi ,

Thanks for the reply . I have removed all the latches in the design. I have warning free synthesis. I see this in the hardware, in the LCD disply of the ML605 board.

I have a charcter mapping code to display 0-9 and A-F. I see that to what ever value i change the bits of SFD. my OP is always either "O" or "?" characters..  These correspond to the CGROM character values "00111111" and "01001111" .. 

I am not sure where i m going wrong .  Is there something else i m missing?

Thanks,

Venkat.

[bwiec]

I would recommend that you do some simulations. If not, you at least need to get chipscope in there. It's hard to debug without being able to see what is going on.

[eteam00]

This might be a good time to run ISIM.  Logic simulation should sort out what your code is generating vs. what you expect to generate.

I assume you have a copy of the LCD controller datasheet, for clear direction on interface protocol and timing.  If not, see this post.

-- Bob Elkind

[venkat_vs2k2]

Hi,,

Thanks for the replies. I have done simulations in ISIM and the behaviroural simulations seems to be fine. I get what i need. May be its time to do some Post-route simulations or use Chipscope to see whats going on in there. I ll post back the status.

Thanks,

Venkat.

[eteam00]

From the ML605 User Guide: "The data interface to the LCD is connected to the FPGA to support 4-bit mode only."

Are you sure that you are setting the LCD controller to 4-bit mode?  The power-on default is 8-bit mode.  This is covered in the LCD controller datasheet.

-- Bob Elkind