05-15-2011 01:41 PM
Has anyone gotten the DDR3 interface working reliably on the ML605 board for an extended amount of time?
I had very little problems with writing and reading good data the first few months after I had purchased the board. But now, it is impossible to get reliable/correct data out of the onboard DDR3 memory. My user interface to the Xilinx memory controller follows the waveforms shown in UG406 pgs 95-99 perfectly. It is also conservative on giving enough setup time between valid app_rdy and stable app_cmd and app_addr signals. There is also a couple of clocks between successive DDR3 write commands and also between successive DDR3 read commands.
I have also replaced the actual DDR3 Memory to eliminate as the problem.
06-14-2012 06:28 AM
Same here. Running a simple application which is located to DDR mem (heap+stack+text) does not work reliably at 100MHz...sporadically the write operations are going wild...
Did you find any solution?