Xilinx Boards and Kits

[tklau]

Using the default *.svf, the programmable clock generator (IDT 5V9885T) on ML505 board cannot generate the 200MHz differential pair as stated in the specifications (UG347, pp.20).

I directly probed all the pins on the clock generator (5V9885T) on the board, all other output frequencies (33MHz, 27MHz, 25MHz) are correct except the 200MHz differential pairs (pin15,16).

Any idea on this issue?

[eteam00]

Apologies for asking the seemingly obvious, but did you follow the programming instructions in UG347 Appendix B?

NOTE: Missing from the instructions in Appendix B is that jumper J14 must be installed.  J14 is located on the component (top) side of the board where the CF card is located.

-- Bob Elkind

[tklau]

Thanks for the prompt reply.

Yes, followed appendix B, with J14 installed. No complaints from iMPACT on the execution of *.svf. Just that no such 200MHz differerntial pair from the clock generator.

[eteam00]

There are a few far-fetched possibilities which need to be ruled out:

• The FPGA is driving the clock input lines from the clock generator.
• The FPGA is re-programming (re-configuring) the clock generator.
• The FPGA is driving the I2C link connected to (and interfering with) the JTAG port which programs the IDT5V9885 device.

These possibilities can be quickly and easily proven wrong by strapping the FPGA configuration mode pins for SLAVE SERIAL.  This should prevent the FPGA from configuring, from driving the clock inputs, interfering with the JTAG re-programming of the IDT5V9885 device, or re-configuring the IDT5V9885 device.

1. Set SW3 positions 4-6 CLOSED (FPGA M0-2 pins strapped for SLAVE SERIAL configuration mode)
2. Power cycle the board (to leave the FPGA in unconfigured state).
3. Re-program the IDT5V9885 device.
4. Power cycle the board again.
5. Verify the signals on pins 15 and 16 of the clock generator.

Are the outputs DC or oscillating at the wrong frequency?  Are pins 15 and 16 behaving as a complementary pair?

If none of this works, the IDT5V9885 device probably needs to be replaced (unless the .SWF file is bogus).

-- Bob Elkind

[gszakacs · Accepted solution]

Just another obvious question that needs to be asked - what's the bandwidth of your scope?

-- Gabor

[eteam00]

Just another obvious question that needs to be asked - what's the bandwidth of your scope?

Yet another obvious question --  Do you realise that

• The single ended IDT5V9885 outputs are using LVTTL voltage swings (2-3 V).
• The IDT5V9885 differential outputs use much smaller voltage swings (300-450 mV) of LVDS or LVPECL.

Using the default *.svf, the programmable clock generator (IDT 5V9885T) on ML505 board cannot generate the 200MHz differential pair as stated in the specifications (UG347, pp.20).

What tests did you perform to determine this?  What does 'cannot generate' mean, specifically?

-- Bob Elkind

[tklau]

Thank you all!

The bandwidth of my scope cannot reach 200MHz, so I wrote some codes and run it on the board (ML505) to verify that 200MHz DS outputs.

The default SVF file for the IDT5V9885 (U8) is correct!

The following may be a bit off-topic: I tried to use the IDT's configration software to generate another SVF for the same frequency outputs as U8's default setting, but after I successfully executed the new SVF via iMPACT, U8 does not output any signals on all channels (1 to 6). These SVF and IDT project file are attached.

Anyone successfully used that tool to alter ML505-U8's setting?

[tklau]

Thank you all!

The bandwidth of my scope cannot reach 200MHz, so I wrote some codes and run it on the board (ML505) to verify that 200MHz DS outputs.

The default SVF file for the IDT5V9885 (U8) is correct!

The following may be a bit off-topic: I tried to use the IDT's configration software to generate another SVF for the same frequency outputs as U8's default setting, but after I successfully executed the new SVF via iMPACT, U8 does not output any signals on all channels (1 to 6). These SVF and IDT project file are attached.

Anyone successfully used that tool to alter ML505-U8's setting?

[jai_pandey]

Dear Friends, I am also working on the same problem. I have used BSB to create MPMC and other required peripheral. BSB also generates UCF for the DDR2 so I think MIG is NOT Required for DDR2. BSB also initializes clock generator to generate 200MHz and other required clocks. So could you please let us know that what is the need of 200MHz differential pair ? regards J

[eteam00]

Jai,

Your problem is unrelated to this thread.  Rather than mix multiple discussion topics in a single thread, please start a new thread.  See item #4 of the "mini-FAQ" in the "signature" text which appears at the bottom of this post.

When you are posting to a new thread, please consider searching UG086 for occurrences of the text string "clk200", and read the contexts in which this string appears.

-- Bob Elkind