Xilinx Boards and Kits

[a_saberi]

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],

  In the paper, I need to implement carrier (multiplying signal with a Since-Cosine function) and the element that is used for it DDS-compiler 3.0. I want to produce frequencies of +/-2000Hz, and I need 8192 sample per period to keep my calculations correct. There are too many parameters to play with and Google a lot and test them for the last 7 days and totally exhausted.

There are at lease FOUR parameters to set at DDS-compiler 3.0

and these are the facts that I have to implement:

=========================================

-The main input signal in between [-4 KHz to 4 KHz] for simplicity consider it f=500Hz but it must limit into this bandwidth.

So,I I'm sampling my input by this sampling rate [T=1/8192] that is the closet power of two to his range and come from Nyquist theory.

- The carried shoud be made by DDS-3.0, nothing else is supported by this board. and It should be able to produce +/- 2000Hz with the sample sampling rate of 1/8192

Please give me some help to be able to forward this project.

Thanks a lot

[ywu]

Take a look at the blog below to see if it helps

DDS in System Generator: how to set up periods?

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a_saberi wrote:

HI Xilinx team,

   I am using Vertex5-LM506. And I'm trying to implement "Digital TDM-FDM translator with multistage structure" which is telecommunication one. by Xilinx package on simulink [MATLAB],

  In the paper, I need to implement carrier (multiplying signal with a Since-Cosine function) and the element that is used for it DDS-compiler 3.0. I want to produce frequencies of +/-2000Hz, and I need 8192 sample per period to keep my calculations correct. There are too many parameters to play with and Google a lot and test them for the last 7 days and totally exhausted.

There are at lease FOUR parameters to set at DDS-compiler 3.0

and these are the facts that I have to implement:

=========================================

-The main input signal in between [-4 KHz to 4 KHz] for simplicity consider it f=500Hz but it must limit into this bandwidth.

So,I I'm sampling my input by this sampling rate [T=1/8192] that is the closet power of two to his range and come from Nyquist theory.

- The carried shoud be made by DDS-3.0, nothing else is supported by this board. and It should be able to produce +/- 2000Hz with the sample sampling rate of 1/8192

Please give me some help to be able to forward this project.

Thanks a lot

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[a_saberi]

thanks Jim;

this is versy uselful