Xilinx Boards and Kits

[asimons]

I am trying to understand how much bandwidth there is between the FPGA and SDRAM on this board.  The SP605 hardware user guide states that there is 667 Mb/s bandwidth.  However, in the Spartan-6 Memory Controller Guide UG388, it says the Spartan 6 has 12.8 Gb/s bandwidth to DDR3 with a 16-bit bus, which I believe the SP605 uses.  Why is there this disconnect?  What am I missing?  Thanks!

Alan Simons

[eteam00]

667 Mb/s bandwidth is the operating speed of the SP605 board design and SP605 board memory.

12.8 Gb/s bandwidth is the maximum memory clock speed (800 MHz) of the fastest speed grade Spartan-6 (-3) multiplied by 16 bits.  This is (more or less) a datasheet specification for the Spartan-6 family, not a specification for a specific circuit board implementation.

-- Bob Elkind

[asimons]

Now, the SP605 apparently has a 16-bit interface to SDRAM.  Does that mean I get 16 * 667 Mb/s?

Alan

[eteam00]

Now, the SP605 apparently has a 16-bit interface to SDRAM.  Does that mean I get 16 * 667 Mb/s?

It means you can achieve *up to* 16 * 667Mb/sec transfer bandwidth between the FPGA and DRAM.

How often and how persistently you can realise this bandwidth is largely determined by the MCB, the DRAM, and your access pattern.  You should expect less than half that bandwidth for typical applications, and around 80% of that bandwidth for specialised applications (e.g. video) with highly structured addressing patterns.

-- Bob Elkind

[asimons]

My problem is reasoning with a coworker about memory bandwidth.  The documentation simply says 667 Mb/s memory bandwidth, which would be 83 MBytes / sec by some logic and this is what he is saying we can get.  I know from past experience that I got much more bandwidth than that on a Spartan-6 LT150X board.  I'm trying to specifically find what the maximum bandwidth this board can support is, but none of the docs just say it.  If there really is a "* 16" factor to the numbers, that's great.  I just want to see some doc that specifically says it.

Alan

[mcgett]

Have your coworker look at Table 1-1 in the Spartan-6 MCB User Guide, UG388, that should clear up their misunderstanding.

[eteam00 · Accepted solution]

The documentation

The 'documentation' in this case is the SP605 Hardware User Guide UG526.  We (me, at least) are easily confused in this forum, so please don't spare essential details.

simply says 667 Mb/s memory bandwidth, which would be 83 MBytes / sec by some logic

A more correct specification is 667 MTransfers/sec.  Using a 16bit DRAM, this would translate to 1333 MBytes/sec.

I'm trying to specifically find what the maximum bandwidth this board can support is, but none of the docs just say it.

The answer, per UG526 version 1.6, is 1333 MBytes/sec.  This is based on the statement on page 13 of UG526:

"The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 667 Mb/s for DDR3 memory in a -3 speed grade device."

The User Guide leaves the x16 multiplication to the user.  Is this confusing?  Possibly, but most people using the SP605 board understand DRAM usage enough to figure it out.  For instance, 64-bit DIMM modules for PCs are specified and compared by both speed grade (e.g. DDR2-667, DDR3-1066) and transfer bandwidth (e.g. PC2-5300, PC3-8500).

Having said that, Xilinx updated the Spartan-6 datasheet (DS162) as of version 2.1 to increase the DDR3 'standard' guaranteed performance of -3 speed grade parts.  The current guaranteed spec is 800Mbits/sec (800MT/sec), per DS162 Table 25.

If you are starting a new design for the SP605 (which uses a -3 speed grade FPGA), using the current ISE (and MIG) software and speed files, the SP605 supports up to DDR3-800 operation (i.e. 1600 MBytes/sec).  The SP605 HW User Guide is out of date (incorrect) in this important and useful specification.

-- Bob Elkind

[eteam00]

I've opened webcase #888616 to update UG526, page 13, as follows:

UG526 v1.6, page 13 includes the following statement:

"The SP605 board supports the “standard” VCCINT setting of 1.20V ± 5%. This setting provides the standard memory controller block (MCB) performance of 667 Mb/s for DDR3 memory in a -3 speed grade device."

As of DS162 v2.1, DDR3 memory (MCB) performance in -3 speed grade parts is 800Mb/s, not 667Mb/sec -- and there is no distinct performance range or setting for DDR3 memory (only for DDR2 memory).

Also, because the SP605 DRAM is 16 bits wide, the 800 (or 667) Mb/sec figure is misleading. SP605 DRAM bandwidth should be re-stated as either 800 MT/sec (transfers/sec) or 1600 MB/sec (bytes/sec).

Change UG526 page 13 text to read:
"The SP605 board supports memory controller block (MCB) performance of 800 MT/s (or 1600 MBytes/sec with 16-bit memory) for DDR3 memory in a -3 speed grade device."

-- Bob Elkind

[eteam00]

Pursuant to webcase #888616,

CR 622620 is filed against UG526

This should update UG526 to reflect that SP605 board supports up to DDR3-800 operation.

-- Bob Elkind

[amandaw]

The wording of UG526 bears revision but it's incorrect to state that an SP605 can be guaranteed at 800MT/s. 

The SP605 is tested at 667MT/s.  At the time the doc was written, it spoke for the MCB accurately but now it simply speaks for the board itself.

ETA: http://www.xilinx.com/support/answers/35818.htm