Xilinx Boards and Kits

[eteam00]

The wording of UG526 bears revision but it's incorrect to state that an SP605 can be guaranteed at 800MT/s.

I believe that might change, soon.  This is the point of the webcase and CR.

The SP605 is tested at 667MT/s.  At the time the doc was written, it spoke for the MCB accurately but now it simply speaks for the board itself.

It should still speak for the MCB.  MCB performance has been updated, and a board which

• uses the -3 speed grade Spartan-6 device
• uses DDR3 device which supports DDR3-800 operation
• is designed to the guidelines of UG388
• uses a MIG-generated MCB-based controller
• otherwise complies with all other DS621 requirements (power supply, etc.)

should be guaranteed by Xilinx to support DDR3-800.

Xilinx' performance guarantee is not based on characterisation of each custom board design, it is based on characterisation of the components (see list above) and design requirements which are used to build the custom board design.  Xilinx customers rely on this guarantee.  Why is the SP605 board any different?

To not extend the SP605 spec represents a disbelief in Xilinx' own datasheet guarantees.  This would -- and should -- raise strong concerns in designers (i.e. customers).

Should the SP605 be tested at DDR3-800?  Absolutely.

Do you think re-rating the SP605 board without testing is a leap of faith?  If so, it is the same leap of faith Xilinx is asking its customers to take when basing their designs on Spartan-6 devices, Xilinx specs, and Xilinx guidelines.

The AR to which Amandaw linked refers to standard vs. enhanced performance distinction for DDR2 (and only DDR2) MCB controllers (see DS162, Table 25). SP605 uses DDR3, not DDR2.

-- Bob Elkind

[mcgett]

> Why is the SP605 board any different?

The SP605 board is a system and not just the silicon and the DDR3 performance is for the entire system.  When we completed all of the testing on the board is was done with the 667 Mbps data rate and all of the reference designs and documentation are geared to this data rate. 

Much later after additional characterization and testing of the Spartan-6 MCB the performance levels were raised to 800 Mbps.   We considered the work involved to accomplish the design updates, re-testing, test program updates, documentation rewrites and reference design releases and made the decision to leave the SP605 at the 667 Mbps level. 

[eteam00]

Ed,

Agreed that the reference (firmware) design, and docs for the reference (firmware) designs, are DDR3-667.

The SP605 board should support new (customer-supplied) FPGA designs -- based on MIG/MCB -- which run at DDR-800 speed.  In other words, SP605 circuit board should be suitable as a hardware platform for developing and proving DDR3-800 designs.

I suspect (just guessing) that a re-MIG-gen of the reference SP605 design should also run DDR3-800 with little or no problems.  Unlike the MIG-generated DRAM controllers targeted for Virtex devices, there is no fixed clock frequency relationship between the controller's UI port(s) and the DRAM.

-- Bob Elkind

[eteam00]

Ed,

The last thing I want to do in life is to annoy you, and I suspect that I'm on the verge of doing just that.  It's not my intent, for what it's worth.

Proposition:

If the SP605 team had determined from the outset to design a DDR3-800 capable board, with the current DS621 specifications in hand, not a single trace of the SP605 circuit board would have turned out differently from the SP605 which is currently documented as a DDR3-667 capable board.

The same design rules, layout rules, and components would have been used.

I concede the point that it is foolhardy to specify a product capability which has not been tested to the standards of the firm.  I wouldn't do it, and no-one should expect Xilinx to do it (my previous posts in this thread notwithstanding).

This raises an interesting question, one which likely extends beyond the original intent and purpose of this thread.  I'll try to articulate this question clearly, but I may not be fully up to the task, so I beg your indulgence.

A hypothetical designer is developing a product which depends upon DDR3-800 capability, and incorporates the same pieces and bits specified and described by Xilinx docs as the SP605.  The company developing this product does not have the capabilities or resources to test worst-case Spartan-6 silicon and worst-case DRAM silicon for DDR3-800 competency.  Any test regime short of full characterisation suites is arguably incomplete.

Can this company honestly warrant its product to DDR3-800 performance, based firmly on the assurance: that Xilinx performed the rigorous characterisation testing of the design components used to construct the final product?  Can the company claim with confidence that its product meets performance specs, on the basis of 'correct-by-construction' ?  If not, then what testing is this company obligated to perform before committing its treasure and reputation to production?

In short, what are designers to make of the DS621 specifications and UG388 guidelines, as they apply to their own Spartan-6 based board designs?

Thank you for your patience.  I understand your viewpoint, and I hope I've expressed mine clearly enough that you understand my viewpoint as a designer.  In large part, I suspect, our interests are much the same.

-- Bob Elkind