Xilinx Boards and Kits

[serge.kubera@ehb.be]

Hi,

I have been trying to communicate with the platform flash on a ML405 board (for reading and writing).  I use a microblaze and the xps_SPI core.   the problem is that in the UCF file I had to write extra lines defining the nets for MISO MOSE etc ...  but when trying to download the bitstream, I get the error : "LOC constraint U11 on xps_spi_0_MISO_pin is invalid: No such site on the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'."

I double checked the validity of the pins in the schematics.  So I would try to bipass the error with MAP_LOCWARN. Where can I do that in EDK?

I was also wondering if what I did was actualy possible : I mean:  if it is ok to try to use these pins (see below), or if it would result in a conflict? 

Net xps_spi_0_SCK LOC = U10;
Net xps_spi_0_SCK IOSTANDARD = LVCMOS33;
NET xps_spi_0_MISO_pin LOC = U11;
Net xps_spi_0_MISO_pin IOSTANDARD = LVCMOS33;
NET xps_spi_0_MOSI_pin LOC = R13;
Net xps_spi_0_MOSI_pin IOSTANDARD = LVCMOS33;
NET xps_spi_0_SS_pin<0> LOC = T10;
Net xps_spi_0_SS_pin<0> IOSTANDARD = LVCMOS33;

Thanks,

Serge

[bassman59]

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serge.kubera@ehb.be wrote:

Hi,

I have been trying to communicate with the platform flash on a ML405 board (for reading and writing).  I use a microblaze and the xps_SPI core.   the problem is that in the UCF file I had to write extra lines defining the nets for MISO MOSE etc ...  but when trying to download the bitstream, I get the error : "LOC constraint U11 on xps_spi_0_MISO_pin is invalid: No such site on the device. To bypass this error set the environment variable   'XIL_MAP_LOCWARN'."

I double checked the validity of the pins in the schematics.  So I would try to bipass the error with MAP_LOCWARN. Where can I do that in EDK?

I was also wondering if what I did was actualy possible : I mean:  if it is ok to try to use these pins (see below), or if it would result in a conflict? 

Net xps_spi_0_SCK LOC = U10;
Net xps_spi_0_SCK IOSTANDARD = LVCMOS33;
NET xps_spi_0_MISO_pin LOC = U11;
Net xps_spi_0_MISO_pin IOSTANDARD = LVCMOS33;
NET xps_spi_0_MOSI_pin LOC = R13;
Net xps_spi_0_MOSI_pin IOSTANDARD = LVCMOS33;
NET xps_spi_0_SS_pin<0> LOC = T10;
Net xps_spi_0_SS_pin<0> IOSTANDARD = LVCMOS33;

Thanks,

Serge

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It's possible that you've got other signals in your design that are not explicitly located via LOC in the UCF, and the tools may have assigned them to the same bank as your SPI port. 

If you didn't set IOSTANDARD for those other signals, they default to LVCMOS25 so the bank VCCs conflict. This is one reason why you'll get an invalid-site error.

-a

[serge.kubera@ehb.be]

thanks for reply.   I actualy didn't know that all pins on the same bank has tobe the same (still newbe).

I check out all outputs in XPS and compared them to the UCF file, and they are all defined.   But I did read somewhere that the problem could be because some programming pins cannot be used (and I actualy try to use those SPI pins) or they are not defined as usable.    So I change the environment variables to disable the warnings and I leave the iostandard undefined and then I could upload the bitstream.

But reading the platform flash still fails and I don't know if it's a software or hardware problem.  

Serge 

[mcgett]

The Xilinx Platform Flash XCF32P is not a SPI device.

Also, when you disable warnings about things that are not usable, it rarely makes them usable.

Message Edited by mcgett on 01-21-2010 08:57 AM

[serge.kubera@ehb.be · Accepted solution]

OK, that solves my confusion about platform flash, thanks.