Every Xilinx FPGA has an oscillator which can generate a clock for "master" configuration modes, used for the CCLK output clock. For some (not all) FPGA families, this oscillator can be available for use after configuration has completed, when your design is operating in the FPGA. For example, in the case of Spartan-3e, see DS312 (v3.8) page 112:
The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes.
Note that the CCLK oscillator is spec'd to have a tolerance (variability) of up to +/- 50% !!
Note that the connections of CCLK for configuration may make this "free" oscillator unusable after configuration has completed. You may not want the SPI clock to your flash memory running freely, for example.
Check the FPGA docs for the FPGA you plan to use. The DCM (or MCM or MMCM) may have a frequency synthesizer capability. Looking at the Spartan-3e datasheet, I believe a clock input is required for frequency synthesis. The Spartan-6 family DCM has a free-running oscillator mode which does not require an external clock source. Depending on which FPGA family you are using, you may not need an external clock source... but you may want one. An external clock source is likely to be much more accurate and more stable than an on-chip free-running frequency synthesizer. Check the FPGA family datasheet for synthesizer accuracy/stability specs.
Recommendation: If you are designing a custom FPGA board, include in your design a provision for an external clock source connected to a GCLK FPGA pin. You don't have to use it (or populate it on the board), but it will come in handy if you realise that it is indeed needed.
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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