Xilinx Boards and Kits

[tkdon]

Hello,

So I actually feel a little bad for asking about this... it ought to be so simple, yet I just can't make it work. I'm new to Xilinx.

Development board: Xilinx Spartan3 Starter Board (The one with 7-seg display) from Digilent: http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,799&Prod=S3BOARD
Software: Xilinx SDK 13.1/ Xilinx XPS 13.1.
Problem: Interfacing/using SRAM (ISSI IS61WV25616BLL) with MicroBlaze using the xps_mch_emc IP core. Memory test fails.

This board is not pre-configured as a development board in XPS, so i need to define what FPGA pin connections that are hardwired to the SRAM.

To get this started I thought i would just use a single of the two SRAM banks, i.e. 256x16.
The pin configurations can be seen in http://www.digilentinc.com/Data/Products/S3BOARD/S3BOARD_RM.pdf from page 12 and onwards.

Regarding the SRAM, my system.ucf file contains:

#Address bus
Net fpga_0_Generic_External_Memory_Mem_A_pin<0> LOC=L5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<1> LOC=N3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<2> LOC=M4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<3> LOC=M3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<4> LOC=L4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<5> LOC=G4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<6> LOC=F3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<7> LOC=F4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<8> LOC=E3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<9> LOC=E4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<10> LOC=G5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<11> LOC=H3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<12> LOC=H4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<13> LOC=J4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<14> LOC=J3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<15> LOC=K3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<16> LOC=K5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<17> LOC=L3;

#Chip enable, output enable, write enable, u/l byte select.
Net fpga_0_Generic_External_Memory_Mem_CEN_pin LOC=P7;
Net fpga_0_Generic_External_Memory_Mem_OEN_pin LOC=K4;
Net fpga_0_Generic_External_Memory_Mem_WEN_pin LOC=G3;
Net fpga_0_Generic_External_Memory_Mem_BEN_pin<1> LOC=T4;
Net fpga_0_Generic_External_Memory_Mem_BEN_pin<0> LOC=P6;

#Data bus
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<0> LOC=N7;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<1> LOC=T8;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<2> LOC=R6;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<3> LOC=T5;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<4> LOC=R5;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<5> LOC=C2;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<6> LOC=C1;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<7> LOC=B1;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<8> LOC=D3;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<9> LOC=P8;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<10> LOC=F2;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<11> LOC=H1;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<12> LOC=J2;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<13> LOC=L2;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<14> LOC=P1;
Net fpga_0_Generic_External_Memory_Mem_DQ_pin<15> LOC=R1;

Regarding the SRAM controller, my system.mhs file contains:

BEGIN xps_mch_emc
 PARAMETER INSTANCE = Generic_External_Memory
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 15000
 PARAMETER C_TAVDV_PS_MEM_0 = 15000
 PARAMETER C_THZCE_PS_MEM_0 = 7000
 PARAMETER C_TWC_PS_MEM_0 = 15000
 PARAMETER C_TWP_PS_MEM_0 = 12000
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_MEM0_BASEADDR = 0x84440000
 PARAMETER C_MEM0_HIGHADDR = 0x8447ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RdClk = clk_50_0000MHz
 PORT Mem_A = fpga_0_Generic_External_Memory_Mem_A_pin
 PORT Mem_CEN = fpga_0_Generic_External_Memory_Mem_CEN_pin
 PORT Mem_OEN = fpga_0_Generic_External_Memory_Mem_OEN_pin
 PORT Mem_WEN = fpga_0_Generic_External_Memory_Mem_WEN_pin
 PORT Mem_BEN = fpga_0_Generic_External_Memory_Mem_BEN_pin
 PORT Mem_DQ = fpga_0_Generic_External_Memory_Mem_DQ_pin
END

I noticed the different default timings to be quite relaxed, so i didn't think this would be a problem, but i haven't crosschecked. I have searched the forums, but didn't find anyone really commenting on that.

I exported the design to Xilinx SDK and created a new software project -  and simply just selected the template "Memory tests".
The correct base address for the single SRAM bank is correctly detected to be 0x84440000, and the size is also correct, i.e. 256KB*1024=0x00040000. When the
FPGA is programmed and the program is executed in hardware, the following is sadly returned:

--Starting Memory Test Application--
NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: Generic_External_Memory
    Memory Controller: xps_mch_emc
         Base Address: 0x84440000
                 Size: 0x00040000 bytes
          32-bit test: FAILED!
          16-bit test: FAILED!
           8-bit test: FAILED!
--Memory Test Application Complete--

(The same design also contains a RS232 interface (uartlite), which is defined as stdin/stdout).



Would anyone be so kind to give me a hint on what is wrong? Do I need to use something else than xps_mch_emc?
What I actually want to do down the road is to use both banks, but firstly i would like to get one working.

Thanks.

[ahmeedrady]

I have the same issue can any body reply 

[djudji]

i've had the same problem. The issue comes from the pin location of the address bus :

#Address bus
Net fpga_0_Generic_External_Memory_Mem_A_pin<0> LOC=L5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<1> LOC=N3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<2> LOC=M4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<3> LOC=M3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<4> LOC=L4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<5> LOC=G4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<6> LOC=F3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<7> LOC=F4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<8> LOC=E3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<9> LOC=E4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<10> LOC=G5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<11> LOC=H3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<12> LOC=H4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<13> LOC=J4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<14> LOC=J3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<15> LOC=K3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<16> LOC=K5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<17> LOC=L3;

The correct pin localization is in fact : (but it isn't specify anywhere)

#Address bus
Net fpga_0_Generic_External_Memory_Mem_A_pin<31> LOC=L5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<30> LOC=N3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<29> LOC=M4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<28> LOC=M3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<27> LOC=L4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<26> LOC=G4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<25> LOC=F3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<24> LOC=F4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<23> LOC=E3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<22> LOC=E4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<21> LOC=G5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<20> LOC=H3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<19> LOC=H4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<18> LOC=J4;
Net fpga_0_Generic_External_Memory_Mem_A_pin<17> LOC=J3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<16> LOC=K3;
Net fpga_0_Generic_External_Memory_Mem_A_pin<15> LOC=K5;
Net fpga_0_Generic_External_Memory_Mem_A_pin<14> LOC=L3;