04-24-2012 11:30 PM
i am doing a project in ML402 and i want to display my output in hyperterminal .The synthesis is coming fine.I could download the program succesfully in the kit using impact. but not able to view the output. can any one tell me the procedure for viewing the output.
do i have to modify the clock to view the output.
do i have to write a seperate program for viewing the output. i made the initail settings in the hyperterminal as specified in the userguide (ie setting baud rate etc).
04-25-2012 11:03 PM
so, what kind of interface have you provided in your design to send result data to some PC with Hyperterminal?
Do you have any idea about the interfaces supported by hyperterminal?
Searching the forum for keywords like "Hyperterminal" or "UART" or even "Picoblaze" should answer most of your questions.
Have a nice synthesis
04-26-2012 03:03 AM
et me be specific with my problem.
I have writtena verilog code with testbench(in icarus verilog) for a 2D DCT module which simply accepts 8 x 8 (64 inputs ) one by one at each clcok pulse and computes the coreesponding coefficients(64 coefficients) after some initial time delay at each clock.
I synthesisd the file in ISE and the code is sythesizable .I could download the bit file using IMPACT but could view the output.
So while searching for the options to view the output i understood tht tthe code can be added as a custom ip and the output can be viewed in hyperterminal or LCD or LED using XPS.
I have no idea how to implement the above three. my doubts are
(1)Which is the best option for my code?
(2_ Is it possible to display my output(64 vaues which is coming at each clcok puse consecutively ) in the hyperterminal?. I have seen some turorial to add a custom IP to microblaze using EDK but i couldnt do it. i really dont know what all ports to use and how. How can i add my verilog code to it.How can i provide my inputs to it. my inputs are 16 bit pixel values and i have 64 of them given one by one at each clcok pulse.
04-26-2012 04:52 AM
so you stepped in the "I concentrate on the function and end up with some isolated IP-Core" trap.
And now you are entering the world of System Design, with nothing but your freshly born IP-core in your hands.
(Don't worry, you're neither the first nor the only one to make this experience.)
The world of engineering is full of decisions to be made. Here's the next one:
Are you going to build just a hardware testbench for your core now, or do you already need performant data throughput?
The answer to this question roughly determines the workload that lies ahead of you.
You probably can guess that the second option means a lot more work to be done.
In the near future you will have to learn and think about interfaces, IP-cores and controlling schemes to get the data in and out of your core.
And maybe you find out that your core is missing synchronisation signals like e.g. DataValid, ClockEnable, Start, Ready Done etc.. Or do you have such signals on your core? Without it controlling the dataflow is a pain.
So make your decision and maybe you like to provide the entity/module port declaration code of your core, so the effort to controll it from the outside can be estimated.
Have a nice synthesis