hello:
when i use spartan6 LX9 kits , create microblaze project, i choose "pick verilog as preferred language", after generate the XPS sdk file, the ISE13.2 print ERROR information ,suggest me use the following ucf of"PIN mb_system_i/debug_module/debug_module/update_BUFG.O" CLOCK_DEDICATED_ROUTE =
FALSE;" , but when add the information in the ucf file, rerun the project, the ISE reprot the following ERROR
Constraint <PIN
"mb_system_i/debug_module/debug_module/update_BUFG.O" CLOCK_DEDICATED_ROUTE =
FALSE;> [mb_system.ucf(20)]: PIN
"mb_system_i/debug_module/debug_module/update_BUFG.O" not found. Please
verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
IF i choose "pick VHDL as perferred language" the above problems sloved, i don't know the reason, give me some suggestion.
