from the master .ucf file (http://www.xilinx.com/products/boards/ml505/ml505_12.1/docs/ml50x_U1_fpga.ucf), the entries for sram has the following:
...
NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
...
NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V
NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V
....
what is the difference between the two SRAM_CLK? should I connect the clock to both of them?
from the 507 schematics (http://www.xilinx.com/support/documentation/boards_and_kits/ml50x_schematics.pdf), on page 20, the image shows that SRAM_FLASH_A1 is connected to the A0 pin on the SRAM, and there are no SRAM_FLASH_A0 connected to the chip, does that mean I don't need to specify the constraint for that port, since I'm only using the SRAM?
Thanks!
