Xilinx Boards and Kits

[yangqiang_jx]

Hi there,

I don't know somebody has experienced the two problems below.

1. The bitstream (route.bit) generated with procedure on xapp1052 won't work on my ML605. The PC side, tried both PCITree and Windriver, can not detect any new Xilinx 0x10EE PCI device, when the bitstream is programmed to the Virtex-6 with either SystemAce of JTAG. Here PCIe IP core (v1.7) is configured at  gen-1, 8 lanes, 250MHz, and 1KB 32-bit BAR0 (BAR1-BAR5 disabled).

2. I built a separate ISE (v13.3) project, and loaded the BMD files from xapp1052.zip and the new generated PCIe core, ISE reported errors at the step of [Implement Design], when "xilinx_pci_exp_v6_8_lane_ep_ml605_gen1.ucf" from xapp1052 is used. ISE also reports errors with "xilinx_pci_exp_v6_8_lane_ep_ml605_gen2.ucf". The ISE errors are in the attached ISEerrors.txt

I'm extremely appreciative if you can tell what causes the problems. 

Thank you in advance.

qy

[austin]

qy,

I suspect that the version of ISE used for this note, is not the same as the version you are using.  Newer versions ask if you wish to use the latest IP cores, which one should never answer "yes" to as newer versions may not be compatible.

It is very possible that the newer IP cores are not compatible, and are the cause of the errors.

Until all errors are resolved, you will not be able to generate a design.  Only after all errors are removed, or reduced to warnings, will you be able to even test anything.

I would first build the application using the same version of the tools that were used to create it in the first place.

[yangqiang_jx]

Hi Austin,

Great thanks.

I found the problems. The xilinx_pci_exp_v6_8_lane_ep_ml605_gen1.ucf comes with xapp1052 is not compatible with my PCIe IP Core setup which is 8-lane, gen-1, and 250MHz, while the system clock is wired to 100Mhz in this default .ucf.

qy.

[ytshah2006]

I would like to know how did you modified the BMD trn signals for AXI interface.I am trying to do same for V-7 and wanted to make sure that if I follow the "TRN to AXI migration considerations" the BMD design in 1052 will work for V-7.Please advice.