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First thing you must do is make sure that there is no logic between the pad and the register.  If there is then there is no way to pack the register into the IOB.  More than likely this is the issue, but you can also use the constraint IOB on the failing registers.

UCF and NCF Syntax
The basic syntax is:
INST "instance_name" IOB={TRUE|FALSE|FORCE};
See value definitions in VHDL Syntax above.
The following statement instructs the mapper to place the foo/bar instance into an IOB component.
INST "foo/bar" IOB=TRUE;

Here if you use the FORCE then it will either place them in the IOB or error out.  This way you know if it doesn't place the registers because it will not go through the tools all the way.

Again if this fails look to make sure there is no logic between the PAD and the register.

Hi, danders,

I follow your suggestion and it also cannot pack the register in IOB.

I am sure there is no logic between the PADs and the registers.

The registers are FDCE type.

The clock pin of FDCE is clock network, but the reset  pin is a generated reset (from other register).

Is it the cause?

The registers with generated reset input cannot be pack in IOB!?

Thanks!

Maybe a little more information would help.  What FPGA are you using?

Which version of ISE?

Did you look in the FPGA editor to see if the output of the flip-flop

routes somewhere else besides the IOB?  If so you may need to

enable register duplication to allow the flip-flop to be pushed

into the IOB, while a duplicate fabric flip-flop generates the feedback

net for internal use.

Finally some FPGA's have additional requirements for IOB routing

which might prevent a flip-flop from being pushed into the IOB if

the other half of the IOB pair already has too many clock or reset

nets routed to it.

Regards,

Gabor

Hi,

I use VIRTEX-4 and VIRTEX-5.

ISE version is 10.1.03 and 11.1.

I checked the NETLIST and there is no logic between register and IOB.

I will check it with FPGA editor.

Thanks!

Hi

my humble experiance is register packing in IO has always been a feature.

 The IOB =TRUEoption is good, it gives a warning if the register you want is not in the IOB

But I like the IOB=FORCE option for brute force, if it can't do it , it errors and I have to notice.

http://www.xilinx.com/support/answers/35507.htm

Besides logic between the register and the OBUF, look for:

- control set restictions

- fanout greater than 1 (must drive only OBUF)

- Hierarchy restrictions

- Area Group Restrictions

Try a LOC constraint to an OLOGIC site. The resulting Pack error will tell you what's wrong.

Hi,

I use FPGA editor to check these IO cannot pack its register in.

Their IO and OLOGIC are connected just like register output IO.

The difference is they connected node type is "IOBINPUT" of OLOGIC, not "IOBOUTPUT" of OLOGIC as IO pack register in.

What is the difference of "IOBINPUT" and "IOBOUTPUT" of "OLOGIC"?

Thanks!

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boneswu wrote:

Hi,

I use FPGA editor to check these IO cannot pack its register in.

Their IO and OLOGIC are connected just like register output IO.

The difference is they connected node type is "IOBINPUT" of OLOGIC, not "IOBOUTPUT" of OLOGIC as IO pack register in.

What is the difference of "IOBINPUT" and "IOBOUTPUT" of "OLOGIC"?

Thanks!

---

IOBINPUT goes into the IOB, and the resulting signal uses the OLOGIC to go out of the chip.

Chip input comes in through the ILOGIC and goes to general FPGA resources through the IOBOUTPUT.

Hi,

Two questions

1. Is there only IOBINPUT in OLOGIC and IOBOUTPUT in  ILOGIC?

2. If IOB and OLOGIC are abuttment in FPGA editor, does it mean the IOB pack the register in?

    How to determine if the IOB pack the register in FPGA editor?

Thanks a lot!