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Hi, I think the upper limit is around 2800 LUTs or so for Spartan6. But then you have maximize everything on MicroBlaze including caches, MMU, branch target, FPU, ....... A typical system is much...
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3
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0
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05-21-2013
12:13 AM
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Hello, I am trying to share a microblaze BRAM with my VHDL external code. I went through the steps demonstrated in this video tutorial: http://www.youtube.com/watch?v=uMEqWmaX6aE (Xilinx EDK Tutori...
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2
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0
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05-16-2013
11:05 AM
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Hi, I try to use the AXI-DMA-Core to connect my custom steam core with DDR-RAM about the PS-AXI-HP-Interface. But this Core is permanent busy. Some ideas? Thx in advanced. HH
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19
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0
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05-16-2013
03:41 AM
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Hi guys, i have a zedboard with ZYNQ processor running Linux and i would like to interface it with the 8 port E1 framer from maxim. Can anyone please give me some guidllines or overview as to how i...
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11
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0
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05-11-2013
01:06 AM
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Just a stab in the dark. Have you tried re-generating your linker script?
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2
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0
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05-10-2013
11:02 AM
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...binary format bit-file address in the DDR-memory and size. The reconfigurable partition has the AREA_GROUP <name> RESET_AFTER_RECONFIG=TRUE; property set in the UCF-file for the project. The...
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12
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0
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05-07-2013
08:40 AM
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Hello Guys, I have looked up the example of axi cdma in zynq ctt and I want to transfer data from PL to PS. I HAVE CONNECTED my VHDL module ------> BRAM ------>CDMA --------> HIGH PERFORMA...
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9
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0
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05-07-2013
12:52 AM
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I have actually gotten my issue resolved. Just an FYI to anyone else who could have this issue, the StartupClk:JtagClk option is what caused my issue.
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0
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0
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05-06-2013
12:41 PM
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In XPS (and IPI), multiple masters and slaves are supported. Only the coregen version of the Interconnect is limited to one slave device
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3
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05-05-2013
11:50 AM
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Issue 1 was also resolved with change of address, Keith.
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0
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0
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04-25-2013
02:53 AM
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