Hi, When I use Chipscope to read a floating input pin (this pin connects to a MicroSD card slot, but the card is not in slot, and there is no pullup or pulldown resistor inside or outside the FPGA)...
I finally could route IODELAY to work with internal signals. I had to double check the mapping since Xilinx tools connected ILOGIC and IODELAY directly instead of placing one register in between. Tha...
In order to verify the sync between two bRAM instances, I created two instances of Chipscope with the following code: component icon_arbitrator PORT ( CONTROL0 : INOUT STD_LOGIC_VECTOR(35 D...
Hi Muneeb A1. See this thread: http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Problem-in-computing-FFT-in-FPGA/m-p/316433#M16479 A2. Fixed point will use MUCH less resources
I make LOC constraint for IDELAYCTRL in UCF file, and the constraints are stated as follow: INST " /DATA_SYNC_U1/IDELAYCTRL_inst" LOC=IDELAYCTRL_X0Y0; INST " /u_MIG_DDR2/u_ddr2_idela...
Dear Members; I like to ask 2 questions that are related to transceivers on 7 series Kintex devices and SERDES. I am looking into the implementation of coaxpress on these Kintex devices with ...
Hi I'm implementing a Low Pass filter on virtex-6 ML500, and I want to know what solution I have to evaluate the output of my filter , for instance , if I store the output in a ROM( or RAM) created b...
I am using Chipscope to interface with System Monitor on a Virtex6 to measure FPGA power on V_P/V_N. Chipscope only samples on JTAG at intervals of 1 second or larger. Is there a way to sample at sma...
Hi, For my project I am using LVCMOS25 I/O standard with Vcco=2.50V. According do datasheet (ds152) output voltages shoud be: V_OL=0.4V and V_HL=V_cco - 0.4V So the difference between V_HL and V_...
Hello, I am working on implementing readback on a Virtex-6 device ( xc6vlx75tff484-1 ) via a SelectMAP x8 interface using an external microprocessor. The design I am reading back is a system with 9 ...
