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Tag: "gtp"

Recently Tagged

	Subject	Replies	Author	Kudos	Latest Post
	GTPA1_DUAL RX Clock Outputs - which is correct? - ( ‎01-23-2013 10:17 PM ) Spartan® Family FPGAs	0	bitjockey	0	‎01-23-2013 10:17 PM by bitjockey
	Reg using Spartan 6 GTP for implementing FPD Link ... - ( ‎01-22-2013 03:42 AM ) Spartan® Family FPGAs	0	rutali	0	‎01-22-2013 03:42 AM by rutali
	Re: problem when using GTP recovered clock on spar... - ( ‎03-31-2012 02:27 AM ) Spartan® Family FPGAs	0	yetingdd	0	‎03-31-2012 02:27 AM by yetingdd
	Spartan-6 GTP Comma Alignment - ( ‎02-24-2012 04:34 PM ) Connectivity	2	saconnor	0	‎11-06-2012 10:56 PM by richterfhg
	Spartan 6 MGT Power Supply Question - ( ‎12-06-2011 05:30 AM ) Spartan® Family FPGAs	0	polyee13	0	‎12-06-2011 05:30 AM by polyee13
	iBERT CPRI - ( ‎11-14-2011 07:14 AM ) Spartan® Family FPGAs	1	eascheiber	0	‎11-16-2011 02:30 AM by eascheiber
	GTP/GTX CDR configuration - ( ‎11-08-2011 12:55 AM ) Virtex® Family FPGAs	5	marko.mehle	0	‎07-26-2012 05:41 AM by musti
	How to assign a signal (string) to a generic map o... - ( ‎07-18-2011 01:59 AM ) Virtex® Family FPGAs	2	pieterhuyghe	0	‎07-18-2011 03:54 AM by pieterhuyghe
	Spartan-6: Were is BUFIO2 <-> GTP association docu... - ( ‎06-08-2011 11:43 AM ) Spartan® Family FPGAs	1	wfjmueller	0	‎02-05-2013 02:54 PM by mbruno222
	GTP PLL lock issue - ( ‎05-04-2011 02:59 AM ) Spartan® Family FPGAs	3	mechouk	0	‎12-02-2011 10:59 PM by alkey3@sbcglobal.net

Most Tagged

	Subject	Replies	Author	Kudos	Latest Post
	Virtex5 GTP: Reliable transmission without protoco... - ( ‎03-13-2009 01:02 AM ) Virtex® Family FPGAs	5	adam.monostori	0	‎03-19-2009 12:03 AM by adam.monostori
	gtp about rxrecclk_dcm_locked - ( ‎04-13-2009 06:33 AM ) Connectivity	2	seanlj	0	‎02-19-2010 10:03 PM by venkata
	Signal to determine CDR is locked in GTP? - ( ‎03-23-2009 10:36 PM ) Virtex® Family FPGAs	2	dballesteros	0	‎06-11-2010 02:16 PM by ezequielsasky
	Board-to-board Aurora communication - ( ‎02-03-2010 07:30 AM ) Connectivity	3	ksahni	0	‎03-16-2013 06:10 AM by chiyuhao
	CLKIN requirements for GTP Rocket IO configured f... - ( ‎05-06-2009 03:46 AM ) Virtex® Family FPGAs	1	srikanthneelam	0	‎05-06-2009 07:40 AM by mcgett
	Spartan-6 GTP Comma Alignment - ( ‎02-24-2012 04:34 PM ) Connectivity	2	saconnor	0	‎11-06-2012 10:56 PM by richterfhg
	Virtex 5-ML505 Evaluation Board: Configure differe... - ( ‎06-03-2009 07:09 PM ) Virtex® Family FPGAs	1	zincbear	0	‎06-03-2009 09:21 PM by mcgett
	Re: XAUI core at reduced speed, lanes? - ( ‎02-18-2009 09:05 PM ) System Logic	0	dbarrowman	0	‎02-18-2009 09:05 PM by dbarrowman
	lock GTX/GTP Tx serial clock to Rx CDR clock? - ( ‎09-13-2009 10:52 AM ) Virtex® Family FPGAs	3	cfreese	0	‎09-16-2009 03:26 PM by mcgett
	Clocking Issues with ML523 Board - No outputs at T... - ( ‎06-11-2009 05:41 PM ) Xilinx Boards and Kits	1	zincbear	0	‎06-12-2009 01:29 PM by mcgett