I apologize for the naivety, but I can't deduce how to introduce a clock into my VHDL project in ISE. I need a single clock with synchronized 125MHZ and 500MHZ outputs, so I went through the core generator and used the Clocking Wizard to create, what I thought, was a clock resource. I see the result under the design tab, but I can't figure out how to access the outputs from it and link them to my components. Further, I still don't know how to connect the inputs and outputs of my components to those of the FPGA chip.

If it matters, this is supposed to be for a Virtex-6 LX240 (ML605).  I'm doing this while I wait for a reference design to become available and the product to ship, which is why I'm trying to connect pins and clocks up myself.

Hi

A clock source, as in an oscilator ?

You need to provide the signal into your chip / design form outside.

In a test bench, to generate the orriginal clock you do something like,

    process
    begin

        clk <= '0';

        wait for 5 ns;
        clk <= '1';
        wait for 5 ns;
    end process;

this toggles the output 'clk' every 5 ns, giving a 10 ns period, i.e. 100 MHz.

Please remeber this is only in a test bench, this can NOT be synthesised to go into the FPGA.

Thanks. I did have a working testbench already. Since synthesizing and simulating are different I wanted to make sure my project was correct by synthesizing, placing, and routing it, and also running some post synthesis simulations. If I wait for the ML605 reference designs to come out, who knows how far off my design could be from what can by synthesized. However, when I try to synthesize I'm told there's no clock, and therefore all of my entities are eliminated from the design.

If I need to provide the signal from outside, I assume that it comes in on some pin, and then the Xilinx clock wizard is for giving me whatever frequency I need out of that. Besides actually getting a clock signal into my project, I'm worried about whether or not ISE will be smart enough to automatically route the clock signal over the low skew pathways specifically designed for clock signals, and... well... I'm just worried in general that I'm doing things correctly. I want to make sure I both get a clock signal in, and that I get it in the right way. First, however, how do I get it in so that I can synthesize my project?

Thanks!

Hi

Ok, clock is just another IO pin of the FPGA.

If your in VHDL, all IO pins will be ports in the top level. And ISE will automatically point them at IO pins.

  Use the UCF file to allocate pins to actual pin number, and also the voltage / drive settings etc.

Very simple approximation,

Is ISE smart, no, like all other synthesisers it's very dumb. 'all' its trying to do is implement the design so that it meets the timing constraints you have set.

  If you set none in the UCF, then synth will just do what it wants to make the design.

Again very simply, if your using global clocks ( as you should unless it's REAL complex ),  clock routing in the FPGA is hard wired,

 So don't worry. Set your constraint in the UCF, period and pin type / placement are the most important ones, and all will be fine.

 Have you worked your way through any of the tutorials available from Xilinx ?

Thanks. Yes, I've watched and read at quite a few of them, unfortunately none that covered how to insert a clock into a design (just what to do, and not to do, with a clock). I'm guessing however, that you know of one which describes exactly that? :) 

I realized I may not have been clear. My design does have a CLK input, what I don't know how to do is connect my CLK input to a real clock. Simulation is no problem, I just set CLK to '1' or '0' every few nanoseconds... Further, I added a memory interface I created with MIG, and I can see it in my project, but I have no idea how to connect it up to my design...

Hi

we're obviously talking at cross putpose here,

If it's not simulation, would use a wire be a good enough answer ?

what board are yopu using ?

Well, unfortunatly, I don't know what "use a wire" means...

I don't yet have a board, or reference design, but it will be the ML605. I created a design from scratch, and I can do unit tests without a problem by driving the clk signal myself using the wait keyword, but I can't get the clock connected to my clk signal when I synthesize because wait is not a synthesizable construct. How do I "use a wire?"

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jonathan.ross wrote:

I realized I may not have been clear. My design does have a CLK input, what I don't know how to do is connect my CLK input to a real clock. Simulation is no problem, I just set CLK to '1' or '0' every few nanoseconds... Further, I added a memory interface I created with MIG, and I can see it in my project, but I have no idea how to connect it up to my design...

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On a real design, the FPGA clock input is a pin that is connected to an external oscillator. This external oscillator is your "real clock."