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Xilinx User Community Forums :
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Ise Error in DDR2 SDRAM Control for Spartan6
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Ise Error in DDR2 SDRAM Control for Spartan6
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dviana
Visitor
Posts: 3
Registered: 11-03-2009
Message 1 of 6
Viewed 263 times
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Hello... I generated a DDR2 SDRAM Memory Control for Spartan6 XC6SLX150T with MIG 3.2 and when I tried to run in ISE I have this error ERROR:LIT:239 - Attribute ARB_TIME_SLOT_0 on MCB instance
"MAIN/example_DDR2/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/samc_0" has
an invalid binary value, "3FFF8".
Checking expanded design ...
The only change I made in VHD given by Xilinx was remove IBufgds in memc3_infrastructure. I used SDC and UCF given in EXample Design. Any idea about what I did wrong... Anybody have a similar situation? Regards Daniel
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11-03-2009 10:22 AM
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Re: Ise Error in DDR2 SDRAM Control for Spartan6
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dviana
Visitor
Posts: 3
Registered: 11-03-2009
Message 3 of 6
Viewed 238 times
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I´m using round robin arbitration... Datasheet Generated by MIG Version 3.2 on ter 3. Nov 19:40:59 2009
FPGA :
Target Device : xc6slx150t-fgg676
Speed Grade : -3
Options :
HDL : VHDL
Synthesis Tool : XST
Module Name : CONTROL_MEMORY_SPARTAN6
No of Controllers : 1
/*******************************************************/
/* Controller 3 */
/*******************************************************/
Interface Parameters :
Frequency : 125
Data Width : 16
Row Address : 13
Column Address : 9
Bank Address : 2
Data Mask : enabled
Memory Configuration : DDR2_SDRAM:Components
Part Number : MT47H16M16XX-3
Supported Part Numbers: MT47H16M16BG-3;MT47H16M16BG-3-IT
Design Parameters :
Mode Register :
Burst Length : 4(010)
Burst Type : sequential
CAS Latency : 3
Mode : normal
DLL Reset : no
PD Mode : fast exit
Write Recovery : 2
Extended Mode Register :
DLL Enable : Enable-Normal
Output Drive Strength : Fullstrength
RTT (nominal) - ODT : 50ohms
Additive Latency (AL) : 0
OCD Operation : OCD Exit
DQS# Enable : Enable
RDQS Enable : Disable
Outputs : Enable
High Temparature Self Refresh Rate : Disable
User Interface Parameters:
Configuration Type: Two 32-bit bi-directional and four 32-bit unidirectional ports
Ports Selected: Port0 Arbitration Algorithm: Round Robin Arbitration:
Time Slot0: 0
Time Slot1: 0
Time Slot2: 0
Time Slot3: 0
Time Slot4: 0
Time Slot5: 0
Time Slot6: 0
Time Slot7: 0
Time Slot8: 0
Time Slot9: 0
Time Slot10: 0
Time Slot11: 0
FPGA Options:
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : UNCALIB_TERM
DQ/DQS : 25 Ohms
Calibration Row Address : 0000
Calibration Column Address : 000
Calibration Bank Address : 0
Bypass Calibration : 1
Debug Signals for Memory Controller : Disable
Thanks for your support!!!
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11-04-2009 02:53 AM
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Re: Ise Error in DDR2 SDRAM Control for Spartan6
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jspaldings
Super Contributor
Posts: 115
Registered: 10-23-2007
Message 6 of 6
Viewed 196 times
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My suggestion is to try the original design with no changes to be sure. I cannot imagine why the removal of the ibufgds would matter, but it is always better to try the unmodified code first. Just generate the design and run ise_flow.bat in the output example_design/par directory. If that passes, make your changes one at a time and see what causes an issue. If ise_flow.bat fails, then you should open a support case because that should not happen. I don't see any connection between the arbitration time slot parameter and ibufgds. I think something else is amiss.
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11-05-2009 11:19 AM
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