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hi there, i have downloaded kcpsm3 for my xc3s700a fpga. But wothout changing anything, i made a project and added files in it, all files of verilog have been added, i am using ISE 11.1. As i add files that are compressed in KCPSM3 rar itself am getting about 450 warnings. Some of them are... WARNING:Xst:616 - Invalid property "XC_PROPS INIT": Did not attach to receive/kcuart/delay15_srl_0. WARNING:Xst:616 - Invalid property "XC_PROPS INIT": Did not attach to processor/reg_loop_register_bit_3.
WARNING:Xst:2591 - "../../../../Verilog/kcuart_rx.v" line 472: attribute on instance <INIT> overrides generic/parameter on entity. It is possible that simulator will not take this attribute into account. WARNING:Xst:2591 - "../../../../Verilog/kcuart_rx.v" line 485: attribute on instance <INIT> overrides generic/parameter on entity. It is possible that simulator will not take this attribute into account.
WARNING:Xst:2591 - "../../../../Verilog/kcuart_rx.v" line 498: attribute on instance <INIT> overrides generic/parameter on entity. It is possible that simulator will not take this attribute into account.
WARNING:Xst:2591 - "kcpsm3.v" line 794: attribute on instance <INIT> overrides generic/parameter on entity. It is possible WARNING:Xst:2591 - "../../../../Verilog/kcuart_tx.v" line 227: attribute on instance <INIT> overrides generic/parameter on entity. It is possible that simulator will not take this attribute into account. this is what i have already tried.. >i have changed the frequency matter... that is author has desgned it for 55MHz and i have 50 MHz on board. >i have read the read me file. It tells to filter the warnings i have filtered them but it cannot be implemented on FPGA >and the last thing i have found is in the read me it has been written that "you should globally replace the directives in the 'kcpsm3' and 'ROM_form' files to match the requirements of your synthesis tool" i dont know how to do this. All have i done by myself is the editing of UCF file which i copied from UART real time clock pdf. and changes the LOC according to my FPGA and synthesize the whole project for both 18ns and 20ns timing constraints. I have tried everything i could. Plz help me. I havent slept a long ago just bcoz of kcpsm3 is giving countless warnings and my impatience is increasing. Plz give a clear cut walkthrough of how to implement fresh copy of UART real time clock project in xilinx ISE widout countless warnings???
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