Hi all,

Simulating my design in modelsim XE III starter shows the following warning

# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.132 ns; Observed := 0.08 ns; At : 2.952 ns
#    Time: 2952 ps  Iteration: 3  Instance: /tb_mydes/uut/a5_sreg1_0_brb2
# ** Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
#   Expected := 0.132 ns; Observed := 0.127 ns; At : 2.991 ns
#    Time: 2991 ps  Iteration: 3  Instance: /tb_mydes/uut/a5_sreg1_2.

 How exactly I can find the solution for this. I am not violating the timing given by xilinx tool. following is the timing details given by xilinx.

   Minimum period: 15.954ns (Maximum Frequency: 62.680MHz)
   Minimum input arrival time before clock: 3.319ns
   Maximum output required time after clock: 4.283ns
   Maximum combinational path delay: No path found

And my test bench timing is default as below

Clock high time : 100 ns

Clock low time : 100 ns

Input setup time : 15 ns

Output Valid Delay : 15 ns

Offset :  100 ns.

Sridar S

Since your clock is running much slower than the reported max frequency, I suspect that

your input timing is not correct in the testbench.  Make sure you are meeting the hold time

required.  You can look at the datasheet report from the post P&R static timing to see

requirements at each pin.  Realise that a hold time violation on an external pin can show

up as a setup time violation in timing simulation.  Essentially the delay on the clock net is

modeled as the maximum delay from timing analysis.  If the data input doesn't meet the

required hold time, it beats the clock to the internal flip-flop by some amount that is

less that the setup time for the flop.

HTH,

Gabor